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pi7c8154a 2-port pci-to-pci bridge revision 1.00 3545 north 1 st street, san jose, ca 95134 telephone: 1-877-pericom, (1-877-737-4266) fax: 408-435-1100 email: solutions@pericom.com internet: http://www.pericom.com
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 2 of 112 july 2004 revision 1.00 life support policy pericom semiconductor corporation? s products are not authorized for use as criti cal components in life support devices or syste ms unless a specific written agreement pertaining to such intended use is executed between the manufactur er and an officer of psc. 1) life support devices or system are devices or systems which: a) are intended for surgical implant into the body or b) support or sustain life and whose failure to perform, when properly used in accordance with instruc tions for use provided in th e labeling, can be reasonably expected to re sult in a significant in jury to the user. 2) a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. pericom semiconductor corporation reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. pericom semiconductor does not assume any responsibility for use of any circuitry described other than the circuitry embodied in a pericom semiconductor product. the company makes no representations that circuitry described herein is free from patent infringement or other rights of thir d parties which may result from its use. no license is granted by implication or otherwise under any pate nt, patent rights or other rights, of pericom semiconductor corporation. all other trademarks are of their respective companies.
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 3 of 112 july 2004 revision 1.00 revision history date revision number description 07/10/04 0.03 initial release of preliminary specification 07/26/04 1.00 initial release of specification to the web updated power dissipation in section 17.9 updated t delay in sections 17.4 and 17.5 revised v ih parameter in section 17.2
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pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 5 of 112 july 2004 revision 1.00 table of contents list of tables................................................................................................................. ..............................10 list of figures................................................................................................................ .............................10 introduction ................................................................................................................... ............................11 1 signal definitions ............................................................................................................. ..............12 1.1 signal types.......................................................................................................................... .......12 1.2 signals ........................................................................................................................ ...................12 1.2.1 primary bus interface signals ........................................................................................12 1.2.2 primary bus interface signal s ? 64-bit ex tension ...................................................14 1.2.3 secondary bus int erface signals ..................................................................................15 1.2.4 secondary bus interface si gnals ? 64-extenstion..................................................17 1.2.5 clock si gnals.................................................................................................................. ........17 1.2.6 miscellaneous signals........................................................................................................18 1.2.7 general purpose i/o interface si gnals.......................................................................19 1.2.8 jtag boundary scan signals .............................................................................................19 1.2.9 power and ground ............................................................................................................... 19 1.3 pin list ........................................................................................................................... .................19 2 signal definitions ............................................................................................................. ..............22 2.1 types of transactions ...........................................................................................................23 2.2 single address phase..............................................................................................................23 2.3 dual address phase.................................................................................................................24 2.4 device select (devsel#) generation ...............................................................................24 2.5 data phase.......................................................................................................................... ..........24 2.6 write transactions ................................................................................................................24 2.6.1 memory write transactions .............................................................................................25 2.6.2 memory write and invalidate..........................................................................................25 2.6.3 delayed write transactions ............................................................................................26 2.6.4 write transaction ad dress boundaries......................................................................27 2.6.5 buffering multiple write transactions ....................................................................27 2.6.6 fast back-to-back transactions ....................................................................................27 2.7 read transactions ..................................................................................................................2 7 2.7.1 prefetchable read transactions ..................................................................................28 2.7.2 non-prefetchable read transactions.........................................................................28 2.7.3 read prefetch address boundaries .............................................................................28 2.7.4 delayed read requests.......................................................................................................29 2.7.5 delayed read completion on target bus ..................................................................29 2.7.6 delayed read completion on initiator bus ..............................................................30 2.7.7 fast back-to-back transactions ....................................................................................31 2.8 configuration transactions ............................................................................................31 2.8.1 type 0 access to pi7c8154a ..................................................................................................31 2.8.2 type 1 to type 0 configuration .......................................................................................32 2.8.3 type 1 to type 1 forwarding .............................................................................................33 2.8.4 special cycles................................................................................................................. ........34 2.9 64-bit operation ...................................................................................................................... ...34 2.9.1 64-bit and 32-bit transactions initiated by pi7c8154a .............................................35 2.9.2 64-bit transactions ? address phase .............................................................................35 2.9.3 64-bit transactions ? data phase ....................................................................................35 2.9.4 64-bit transactions ? received by pi7c8154a ...............................................................36 2.9.5 64-bit transactions ? support during reset..............................................................36
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 6 of 112 july 2004 revision 1.00 2.10 transaction flow through................................................................................................37 2.11 transaction termination....................................................................................................37 2.11.1 master termination initiated by pi7c8154a............................................................38 2.11.2 master abort received by pi7c8154a .........................................................................38 2.11.3 target termination received by pi7c8154a............................................................39 2.11.3.1 delayed write target t ermination response ......................................................39 2.11.3.2 posted write target t ermination response.........................................................41 2.11.3.3 delayed read target t ermination response .......................................................41 2.11.4 target termination initiated by pi7c8154a ............................................................42 2.11.4.1 target retry ................................................................................................................... ....42 2.11.4.2 target disconnect...........................................................................................................43 2.11.4.3 target abort................................................................................................................... ....43 3 address decoding ............................................................................................................... .............43 3.1 address ranges ......................................................................................................................... 44 3.2 i/o address decoding ..............................................................................................................44 3.2.1 i/o base and limit address register ..............................................................................45 3.2.2 isa mode ....................................................................................................................... ..............45 3.3 memory address decoding..................................................................................................46 3.3.1 memory-mapped i/o base and limit address registers..........................................46 3.3.2 prefetchable memory base and limit address registers...................................47 3.3.3 prefetchable memory 64-bit addressing registers ..............................................48 3.4 vga support ........................................................................................................................ .........49 3.4.1 vga mode ....................................................................................................................... ............49 3.4.2 vga snoop mode ................................................................................................................. ....49 4 transaction ordering ........................................................................................................... ......50 4.1 transactions governed by ordering rules ..............................................................50 4.2 general ordering guidelines............................................................................................51 4.3 ordering rules .......................................................................................................................... 51 4.4 data synchronization ..........................................................................................................52 5 error handling ................................................................................................................. ...............53 5.1 address parity errors...........................................................................................................53 5.2 data parity errors..................................................................................................................54 5.2.1 configuration write transactions to configuration space...........................54 5.2.2 read transa ctions .............................................................................................................. ..54 5.2.3 delayed write transactions ............................................................................................55 5.2.4 posted write transactions ...............................................................................................57 5.3 data parity error reporting.............................................................................................58 5.4 system error (serr#) reporting ........................................................................................61 6 exclusive access............................................................................................................... ...............62 6.1 concurrent locks ...................................................................................................................62 6.2 acquiring exclusive access across pi7c8154a ...........................................................62 6.2.1 locked transactions in downstream direction.....................................................62 6.2.2 locked transaction in upstream direction .............................................................64 6.3 ending exclusive access ......................................................................................................64 7 pci bus arbitration............................................................................................................ .............64 7.1 primary pci bus arbitration...............................................................................................65 7.2 secondary pci bus arbitration.........................................................................................65 7.2.1 secondary bus arbitration using the internal arbiter......................................65 7.2.2 preemptio n..................................................................................................................... ..........66
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 7 of 112 july 2004 revision 1.00 7.2.3 secondary bus arbitration using an external arbiter .......................................67 7.2.4 bus parking .................................................................................................................... ..........67 8 general purpose i/o interface ...............................................................................................67 8.1 gpio control registers .........................................................................................................68 8.2 secondary clock control ..................................................................................................68 8.3 live insertion ...................................................................................................................... .......70 9 eeprom interface............................................................................................................... .............70 9.1 auto mode eeprom access....................................................................................................70 9.2 eeprom mode at reset ............................................................................................................71 9.3 eeprom data structure ........................................................................................................71 9.4 eeprom content........................................................................................................................ .71 10 vital product data (vpd) ....................................................................................................... .....72 11 clocks......................................................................................................................... ............................72 11.1 primary and secondary clock inputs...........................................................................72 11.2 secondary clock outputs...................................................................................................72 12 pci power management........................................................................................................... .....72 13 reset.......................................................................................................................... ...............................74 13.1 primary interface reset ......................................................................................................74 13.2 secondary interface reset ................................................................................................74 13.3 chip reset .......................................................................................................................... ............75 14 configuration registers ........................................................................................................ ...76 14.1.1 signal types................................................................................................................... ......77 14.1.2 vendor id register ? offset 00h .................................................................................77 14.1.3 device id register ? offset 00h ...................................................................................77 14.1.4 command register ? offset 04h ..................................................................................77 14.1.5 status register ? offest 04h.........................................................................................78 14.1.6 revision id regist er ? offset 08h................................................................................79 14.1.7 class code regist er ? offset 08h ...............................................................................79 14.1.8 cache line size regi ster ? offset 0ch ......................................................................79 14.1.9 primary latency timer reg ister ? offset 0ch.......................................................79 14.1.10 header type register ? offset 0ch............................................................................80 14.1.11 primary bus number register ? offset 18h ............................................................80 14.1.12 secondary bus number reg ister ? offs et 18h ......................................................80 14.1.13 subordinate bus number register ? offset 18h ..................................................80 14.1.14 secondary latency ti mer ? offset 18h ....................................................................80 14.1.15 i/o base register ? offset 1ch ......................................................................................80 14.1.16 i/o limit register ? offset 1ch.....................................................................................81 14.1.17 secondary status register ? offset 1ch ................................................................81 14.1.18 memory base regist er ? offset 20h ...........................................................................82 14.1.19 memory limit regist er ? offset 20h ..........................................................................82 14.1.20 prefetchable memory base address register ? offset 24h ...........................82 14.1.21 prefetchable memory limit addres s register ? o ffset 24h ..........................83 14.1.22 prefetchable memory base address upper 32-bits register ? offset 28h83 14.1.23 prefetchable memory limit address uppe r 32-bits register ? offset 2ch 83 14.1.24 i/o base address upper 16-bits register ? offset 30h .........................................83 14.1.25 i/o limit address upper 16-bits register ? offset 30h........................................83 14.1.26 capability pointer regis ter ? offset 34h ...............................................................84
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 8 of 112 july 2004 revision 1.00 14.1.27 interrupt line regist er ? offset 3ch .......................................................................84 14.1.28 interrupt pin register ? offset 3ch .........................................................................84 14.1.29 bridge control regist er ? offset 3ch ....................................................................84 14.1.30 diagnostic / chip control register ? offset 40h................................................86 14.1.31 arbiter control regist er ? offset 40h....................................................................86 14.1.32 extended chip control regi ster ? offset 48h.....................................................87 14.1.33 upstream memory control register ? offset 48h..............................................88 14.1.34 secondary bus arbiter preemption control register ? offset 4ch..........88 14.1.35 hot swap switch time slot register ? o ffset 4ch...............................................88 14.1.36 eeprom autoload control / status register ? offset 50h .............................89 14.1.37 eeprom address / control re gister ? offs et 54h ...............................................89 14.1.38 eeprom data register ? offset 54h ...........................................................................89 14.1.39 upstream (s to p) memory base address register ? offset 58h .....................90 14.1.40 upstream (s to p) memory limit address register ? offset 58h ....................90 14.1.41 upstream (s to p) memory base add ress upper 32-bit register ? offset 5ch 90 14.1.42 upstream (s to p) memory limit address upper 32-bit register ? offset 60h 90 14.1.43 p_serr# event disable reg ister ? offset 64h.........................................................90 14.1.44 gpio data and control register ? of fset 64h ......................................................92 14.1.45 secondary clock control re gister ? offset 68h...............................................92 14.1.46 p_serr# status register ? offset 68h........................................................................94 14.1.47 port option regist er ? offset 74h .............................................................................94 14.1.48 secondary master timeout counter register ? offset 80h...........................96 14.1.49 primary master timeout coun ter register ? offset 80h.................................96 14.1.50 capability id regist er ? offset b0h ...........................................................................96 14.1.51 next pointer register ? offset b0h...........................................................................96 14.1.52 slot number register ? offset b0h ...........................................................................96 14.1.53 chassis number regist er ? offset b0h .....................................................................97 14.1.54 capability id register ? offset dch..........................................................................97 14.1.55 next item pointer regi ster ? offset dch ...............................................................97 14.1.56 power management capabilities register ? offset dch .................................97 14.1.57 power management data register ? offset e0h..................................................97 14.1.58 ppb support extensions regi ster ? offset e0h ....................................................98 14.1.59 data register ? offset e0h............................................................................................98 14.1.60 capability id regist er ? offset e4h ...........................................................................98 14.1.61 next pointer register ? offset e4h...........................................................................98 14.1.62 hot swap control and status register ? offset e4h ........................................98 14.1.63 capability id regist er ? offset e8h ...........................................................................99 14.1.64 next pointer register ? offset e8h...........................................................................99 14.1.65 vpd register ? offset e8h ..............................................................................................99 14.1.66 vpd data register ? offset ech ..................................................................................99 15 bridge beh avior ................................................................................................................ .............100 15.1 bridge actions for various cycle types....................................................................100 15.2 abnormal termination (initiated by bridge master) .........................................100 15.2.1 master abort ................................................................................................................... .100 15.2.2 parity and error reporting ......................................................................................100 15.2.3 reporting parity errors .............................................................................................101 15.2.4 secondary idsel mapping............................................................................................101 16 ieee 1149.1 compatible jtag contro ller .........................................................................101 16.1 boundary scan architectu re .........................................................................................101 16.1.1 tap pins ....................................................................................................................... .........102
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 9 of 112 july 2004 revision 1.00 16.1.2 instruction register ....................................................................................................102 16.2 boundary scan instruction set .....................................................................................103 16.3 tap test data registers ......................................................................................................103 16.4 bypass register ....................................................................................................................... 104 16.5 boundary scan register ....................................................................................................104 16.6 tap controller..................................................................................................................... ...104 17 electrical and timing specifications.............................................................................109 17.1 maximum ratings....................................................................................................................109 17.2 dc specifications ................................................................................................................. ...109 17.3 ac specifications ................................................................................................................. ...109 17.4 66mhz pci signaling timing.................................................................................................110 17.5 33mhz pci signaling timing.................................................................................................110 17.6 reset timing......................................................................................................................... ......110 17.7 gpio timing (66mhz & 33mhz) ................................................................................................111 17.8 jtag timing ......................................................................................................................... ........111 17.9 power consumption...............................................................................................................111 18 package information ............................................................................................................ .....112 18.1 304-ball pbga package diagram......................................................................................112 18.2 ordering information .........................................................................................................112
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 10 of 112 july 2004 revision 1.00 list of tables t able 2-1 pci transactions................................................................................................................... .....23 t able 2-2 write transaction forwarding........................................................................................24 t able 2-3 write transaction disconnect address boundaries .............................................27 t able 2-4 read prefetch address boundaries ................................................................................29 t able 2-5 read transaction prefetching .........................................................................................29 t able 2-6 device number to idsel s_ad pin mapping......................................................................33 t able 2-7 delayed write target termination response ...........................................................41 t able 2-8 response to posted write target termination.........................................................41 t able 2-9 response to delayed read target termination.......................................................42 t able 4-1 summary of transaction ordering .................................................................................51 t able 5-1 setting the primary interface detected parity error bit ( bit 31 of offset 04 h ) .............................................................................................................................. ................................58 t able 5-2 setting the secondary interface detected parity error bit ..........................58 t able 5-3 setting the primary interface data parity detected bit ( bit 24 of offset 04 h ) ............................................................................................................................... .......................................59 t able 5-4 setting the secondary interface data parity detected bit.............................59 t able 5-5 assertion of p_perr# ................................................................................................................60 t able 5-6 assertion of s_perr# ................................................................................................................60 t able 5-7 assertion of p_serr# for data parity errors ............................................................61 t able 8-1 gpio operation ...................................................................................................................... ......69 t able 8-2 gpio serial data format........................................................................................................69 t able 12-1 power management transitions.....................................................................................73 t able 14-1 configuration space map....................................................................................................76 t able 16-1 tap pins........................................................................................................................... .............103 t able 16-2 jtag boundary register order......................................................................................105 list of figures f igure 7-1 secondary arbiter example ..............................................................................................66 f igure 16-1 test access port diagram................................................................................................102 f igure 17-1 pci signal timing measurement conditions...........................................................109 f igure 18-1 304-ball pbga package outline .....................................................................................112
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 11 of 112 july 2004 revision 1.00 introduction product description the pi7c8154a is pericom semic onductor?s pci-to-pci bridge, designed to be fully compliant with the 64-bit, 66mhz implementation of the pci local bus specification, revision 2.2. the pi7c8154a supports synchronous bus transactions between devices on the primary bus and the secondary buses operating up to 66mhz. the prim ary and secondary buses can also operate in concurrent mode, resulting in added increase in system performance. product features ! 64-bit primary and secondary ports run up to 66mhz ! compliant with the pci local bus specification, revision 2.2 ! compliant with pci-to-pci bridge architecture specification , revision 1.1 . - all i/o and memory commands - type 1 to type 0 configuration conversion - type 1 to type 1 configuration forwarding - type 1 configuration write to special cycle conversion ! compliant with the pci power management specification, revision 1.1 ! provides internal arbitration fo r four secondary bus masters - programmable 2-level priority arbiter ! supports serial eeprom interface fo r register auto-load and vpd access ! dynamic prefetching control ! supports posted write buffers in all directions ! 512 byte upstream posted memory write ! 512 byte downstream posted memory write ! 1024 byte upstream read data buffer ! 1024 byte downstream read data buffer ! enhanced address decoding ! 32-bit i/o address range ! 32-bit memory-mapped i/o address range ! 64-bit prefetchable address range ! ieee 1149.1 jtag interface support ! extended commercial temperature range 0c to 85c ! 3.3v and 5v signaling ! 304-pin pbga package - pb-free & green available
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 12 of 112 july 2004 revision 1.00 1 signal definitions 1.1 signal types signal type description i input only o output only p power ts tri-state bi-directional sts sustained tri-state. active low signal must be pulled high for 1 cy cle when deasserting. od open drain 1.2 signals note: signal names that end with ?#? are active low. 1.2.1 primary bus interface signals name pin # type description p_ad[31:0] u2, u4, u1, v2, v1, v3, w2, w1, w4, y3, aa1, aa3, y4, ab3, aa4, y5, ab8, aa8, ac9, ab9, aa9, ac10, aa10, y11, ab11, aa11, aa12, ab12, ab13, aa13, y13, aa14 ts primary address / data: multiplexed address and data bus. address is indicated by p_frame# assertion. write data is stable and valid when p_irdy# is asserted and read data is stable and valid when p_trdy# is asserted. data is transferred on rising clock edges when both p_irdy# and p_trdy# are asserted. during bus idle, bridge drives p_ad[31:0] to a valid logic level when p_gnt# is asserted. p_cbe[3:0] y2, ab4, aa7, ac11 ts primary command/byte enables: multiplexed command field and byte enable field. during address phase, the initiator drives the transaction type on these pins. after that , the initiator drives the byte enables during data phases. during bus idle, bridge drives p_cbe[3:0] to a valid logic level when p_gnt# is asserted. p_par ab7 ts primary parity. p_par is even parity of p_ad[31:0] and p_cbe[3:0] (i.e. an even number of 1?s). p_par is valid and stable one cycle after the address phase (indicated by assertion of p_frame#) for address pa rity. for write data phases, p_par is valid one clock after p_irdy# is asserted. for read data phase, p_par is valid one clock after p_trdy# is asserted. signal p_par is tri-stated one cycle after the p_ad lines are tri- stated. during bus idle, bridge drives p_par to a valid logic level when p_gnt# is asserted. p_frame# aa5 sts primary frame (active low). driven by the initiator of a transaction to indicate the beginning and duration of an access. the de-assertion of p_frame# indicates the final data phase requested by the initiator. before be ing tri-stated, it is driven to a de-asserted state for one cycle.
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 13 of 112 july 2004 revision 1.00 name pin # type description p_irdy# ac5 sts primary irdy (active low). driven by the initiator of a transaction to indicate its ability to complete current data phase on the primary side. once asserted in a data phase, it is not de-asserted until the end of the data phase. before tri-stated, it is driven to a de-asserted state for one cycle. p_trdy# ab5 sts primary trdy (active low). driven by the target of a transaction to indicate its ability to complete current data phase on the primary side. once asserted in a data phase, it is not de-asserted until the end of the data phase. before tri-stated, it is driven to a de-asserted state for one cycle. p_devsel# aa6 sts primary device select (active low). asserted by the target indicating that the device is accepting the transaction. as a master, bridge waits for the assertion of this signal within 5 cycles of p_frame# assertion; otherwise, terminate with master abort. before tri-stated, it is driven to a de-asserted state for one cycle. p_stop# ac6 sts primary stop (active low). asserted by the target indicating that the target is requesting the initiator to stop the current transaction. before tri- stated, it is driven to a de-asserted state for one cycle. p_lock# ab6 i primary lock (active low). asserted by an initiator, one clock cycle af ter the first address phase of a transaction, attempting to perform an operation that may take more than one pci transaction to complete. p_idsel y1 i primary id select. used as a chip select line for type 0 configuration access to bridge configuration space. p_perr# ac7 sts primary parity error (active low). asserted when a data parity error is detected for data received on the primary interface. before being tri-stated, it is driven to a de-asserted state for one cycle. p_serr# y7 od primary system error (active low). can be driven low by any device to indicate a system error condition. bridge drives this pin on: ! address parity error ! posted write data par ity error on target bus ! secondary s_serr# asserted ! master abort during posted write transaction ! target abort during posted write transaction ! posted write transaction discarded ! delayed write request discarded ! delayed read request discarded ! delayed transaction master timeout this signal requires an external pull-up resistor for proper operation. p_req# u3 ts primary request (active low): this is asserted by bridge to indicate that it wants to start a transaction on the primary bus. bridge de-asserts this pin for at least 2 pci clock cycles before asserting it again. p_gnt# r2 i primary grant (active low): when asserted, pi7c8154a can access the primary bus. during idle and p_gnt# asserted, bridge will drive p_ad, p_cbe, and p_par to valid logic levels. p_reset# r3 i primary reset (active low): when p_reset# is active, all pci signals should be asynchronously tri-stated.
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 14 of 112 july 2004 revision 1.00 name pin # type description p_m66en ab10 i primary interface 66mhz operation. this input is used to specify if bridge is capable of running at 66mhz. for 66mhz operation on the primary bus, this signal should be pulled ?high?. for 33mhz operation on the primary bus, this signal should be pulled ?low?. in this condition, s_m66en will be driven ?low?, forcing the secondary bus to run at 33mhz also. 1.2.2 primary bus interface signals ? 64-bit extension name pin # type description p_ad[63:32] aa16, ab16, aa17, ab17, y17, ab18, ac18, aa18, ac19, aa19, ab20, y19, aa20, ab21, ac21, aa21, y20, aa23, y21, w20, y23, w21, w23, w22, v21, v23, v22, u23, u20, u22, t23, t22 ts primary upper 32-bit address / data: multiplexed address and data bus providing an additional 32 bits to the primary. when a dual address command is used and p_req64# is asserted, the initiator drives the upper 32 bits of the 64-bit address. otherwise, these bits are undefined and driven to valid logic levels. during the data phase of a transaction, th e initiator drives the upper 32 bits of the 64-bit write da ta, or the target drives the upper 32 bits of the 64-bit read data, when p_req64# and p_ack64# are both asserted. otherwise, these bits are pulled up to a valid logic level through external resistors. p_cbe[7:4] aa15, ab15, y15, ac15 ts primary upper 32-bit command/byte enables: multiplexed command field and byte enable field. during address phase, when the dual address command is used and p_req64# is asserted, the initiator drives the transaction type on these pins. otherwise, these bits are undefined, and the initiator drives a valid logic level onto the pins. for read and write transactions, the initia tor drives these bits for the p_ad[63:32] data bits when p_req64# and p_ack64# are both asserted. when not driven, these bits are pulled up to a valid logic level through external resistors. p_par64 t21 ts primary upper 32-bit parity: p_par64 carries the even parity of p_ad[63:32] and p_cbe[7:4] for both address and data phases. p_par64 is driven by the initiator and is valid 1 cycle after the first address phase when a dual address command is used and p_req64# is asserted. p_par64 is valid 1 clock cycle after the second address phase of a dual address transaction when p_req64# is asserted. p_par64 is valid 1 cycle af ter valid data is driven when both p_req64# and p_ack64# are asserted for that data phase. p_par64 is driven by the device driving read or write data 1 cycle after the p_ad lines are driven. p_par64 is tri-stated 1 cycle after the p_ad lines are tri-stated. devices receive data sample p_par64 as an input to check for possible parity errors during 64-bit transactions. when not driven, p_par64 is pulled up to a valid logic level through external resistors.
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 15 of 112 july 2004 revision 1.00 name pin # type description p_req64# ac14 sts primary 64-bit transfer request: p_req64# is asserted by the initiator to indicate that the initiator is requesting a 64-bit data transfer. p_req64# has the same timing as p_frame#. when p_req64# is asserted low during reset, a 64-bit data path is supported. when p_req64# is high during reset, bridge drives p_ad[63:32], p_cbe[7:4], and p_par64 to valid logic levels. when deasserting, p_req64# is driven to a deasserted state for 1 cycle and then sustained by an external pull-up resistor. p_ack64# ab14 sts primary 64-bit transfer acknowledge: p_ack64# is asserted by the target only when p_req64# is asserted by th e initiator to indicate the target?s ability to transf er data using 64 bits. p_ack64# has the same timing as p_devsel#. when deasserting, p_ack64# is driven to a deasserted state for 1 cycle and then is sustained by an external pull-up resistor. 1.2.3 secondary bus interface signals name pin # type description s_ad[31:0] c3, a3, b3, c4, a4, b4, c5, b5, a6, a7, d7, b7, a8, b8, c8, a9, c13, b13, a13, d13, c14, b14, c15, b15, c16, b16, c17, b17, d17, a17, b18, a18 ts secondary address/data: multiplexed address and data bus. address is indicated by s_frame# assertion. write data is stable and valid when s_irdy# is asserted and read data is stable and valid when s_irdy# is asserted. data is transferred on rising clock edges when both s_irdy# and s_trdy# are asserted. during bus idle, bridge drives s_ad[31:0] to a valid logic level when s_gnt# is asse rted respectively. s_cbe[3:0] c6, d9, c12, a15 ts secondary command/byte enables: multiplexed command field and byte enable field. during address phase, the initiator drives the transaction type on these pins. the initia tor then drives the byte enables during data phases. during bus idle, bridge drives s_cbe[3:0] to a va lid logic level when the internal grant is asserted. s_par b12 ts secondary parity: s_par is an even parity of s_ad[31:0] and s_cbe[3:0] (i.e. an even number of 1?s). s_par is valid and stable one cycle after the address phase (indicated by assertion of s_frame#) for address pa rity. for write data phases, s_par is valid one clock after s_irdy# is asserted. for read data phase, s_par is valid one clock after s_trdy# is asserted. signal s_par is tri-stated one cycle after the s_ad lines are tri- stated. during bus idle, bridge drives s_par to a valid logic level when the in ternal grant is asserted. s_frame# b9 sts secondary frame (active low): driven by the initiator of a transaction to indicate the beginning and duration of an access. the de-assertion of s_frame# indicates the final data phase requested by the initiator. before be ing tri-stated, it is driven to a de-asserted state for one cycle. s_irdy# c9 sts secondary irdy (active low): driven by the initiator of a transaction to indicate its ability to complete current data phase on the secondary side. once asserted in a data phase, it is not de-asserted until the end of the data phase. before tri-stated, it is driven to a de-asserted state for one cycle.
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 16 of 112 july 2004 revision 1.00 name pin # type description s_trdy# a10 sts secondary trdy (active low): driven by the target of a transaction to indicate its ability to complete current data phase on the secondary side. once asserted in a data phase, it is not de-asserted until the end of the data phase. before tri-stated, it is driven to a de-asserted state for one cycle. s_devsel# b10 sts secondary device select (active low): asserted by the target indicating that the device is accepting the transaction. as a master, bridge waits for the assertion of this signal within 5 cycles of s_frame# assertion; otherwise, terminate with master abort. before tri-stated, it is driven to a de- asserted state for one cycle. s_stop# c10 sts secondary stop (active low): asserted by the target indicating that the target is requesting the initiator to stop the current transaction. before tri- stated, it is driven to a de-asserted state for one cycle. s_lock# a11 sts secondary lock (active low): asserted by an initiator, one clock cycle af ter the first address phase of a transaction, when it is propagating a locked transaction downstream. bridge does not propagate locked transactions upstream. s_perr# c11 sts secondary parity e rror (active low): asserted when a data parity error is detected for data received on the secondary interface. before being tri-stated, it is driven to a de-asserted state for one cycle. s_serr# b11 i secondary system error (active low): can be driven low by any device to indicate a system error condition. s_req#[8:0] e1, e3, d2, d1, e4, d3, c2, c1, d4 i secondary request (active low): this is asserted by an external device to indicate that it wants to start a transaction on the secondary bus. the input is externally pulled up through a resistor to vdd. s_gnt#[8:0] h1, g3, g2, g4, g1, f2, f1, f3, e2 ts secondary grant (active low): pi7c8154a asserts these pins to allow external masters to access the secondary bus. bridge de-asserts these pins for at least 2 pci clock cycles before asserting it again. during idle and s_gnt# deasserted, pi7c8154a will drive s_ad, s_cbe, and s_par. s_reset# h2 o secondary reset (active low): asserted when any of the following conditions are met: 1. signal p_reset# is asserted. 2. secondary reset bit in bri dge control register in configuration space is set. 3. the chip reset bit in the chip control register in configuration space is set. when asserted, all control signals are tri-stated and zeroes are driven on s_ad, s_cbe, s_par, and s_par64. s_m66en a14 i/od secondary interface 66mhz operation: this input is used to specify if bridge is capable of running at 66mhz on the secondary side. when high, the secondary bus may run at 66mhz. when low, the secondary bus may only run at 33mhz. if p_m66en is pulled low, the s_m66en is driven low. s_cfn# k1 i secondary bus central function control pin: when tied low, it enables the internal arbiter. when tied high, an external arbiter must be used. s_req#[0] is reconfigured to be the secondary bus grant input, and s_gnt#[0] is reconfigured to be the secondary bus request output.
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 17 of 112 july 2004 revision 1.00 1.2.4 secondary bus interface signals ? 64-extenstion name pin # type description s_ad[63:32] c20, a21, d20, c21, c23, c22, d21, e20, d22, e21, e23, f21, f23, f22, g20, g22, g21, h23, h22, h21, j23, j20, j22, k23, k22, k21, l23, l21, l22, m22, m23, m21 ts secondary upper 32-bit address/data: multiplexed address and data bus. address is indicated by s_frame# assertion. write data is stable and valid when s_ir dy# is asserted and read data is stable and valid wh en s_irdy# is asserted. data is transferred on rising clock edges when both s_irdy# and s_trdy# are asserted. during bus idle, bridge drives s_ad to a valid logic level when s_gnt# is asserted respectively. s_cbe[7:4] a19, c19, a20, d19 ts secondary upper 32-bit command/byte enables: multiplexed command field and byte enable field. during address phase, the initiator drives the transaction type on these pins. the initiator then drives the byte enables during data phases. during bus idle, bridge drives s_cbe[7:0] to a valid logic level when the internal grant is asserted. s_par64 n21 ts secondary upper 32-bit parity: s_par64 carries the even parity of s_ad[63:32] and s_cbe[7:4] for both address and data phases. s_par64 is driven by the initiator and is valid 1 cycle after the first address phase when a dual address command is used and s_req64# is asserted. s_par64 is valid 1 clock cycle after the second address phase of a dual address transaction when s_req64# is asserted. s_par64 is valid 1 cycle af ter valid data is driven when both s_req64# and s_ack64# are asserted for that data phase. s_par64 is driven by the device driving read or write data 1 cycle after the s_ad lines are driven. s_par64 is tri-stated 1 cycle after the s_ad lines are tri-stated. devices receive data sample s_par64 as an input to check for possible parity errors during 64-bit transactions. when not driven, s_par64 is pulled up to a valid logic level through external resistors. s_req64# b19 sts secondary 64-bit transfer request: s_req64# is asserted by the initiator to indicate that the initiator is requesting a 64-bit data transfer. s_req64# has the same timing as s_frame#. when s_req64# is asserted low during reset, a 64-bit data path is supported. when s_req64# is high during reset, bridge drives s_ad[63:32], s_cbe[7:4], and s_par64 to valid logic levels. when deasserting, s_req64# is driven to a deasserted state for 1 cycle and then sustained by an external pull-up resistor. s_ack64# c18 sts secondary 64-bit transfer acknowledge: s_ack64# is asserted by the target only when s_req64# is asserted by th e initiator to indicate the target?s ability to transf er data using 64 bits. s_ack64# has the same timing as s_devsel#. when deasserting, s_ack64# is driven to a deasserted state for 1 cycle and then is sustained by an external pull-up resistor. 1.2.5 clock signals name pin # type description p_clk t3 i primary clock input: provides timing for all transactions on the primary interface.
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 18 of 112 july 2004 revision 1.00 name pin # type description s_clkin j4 i secondary clock input: provides timing for all transactions on the secondary interface. s_clkout[9:0] p1, p2 , p3, n1, n3, m2, m1, m3, l3, l2 o secondary clock output: provides secondary clocks phase synchronous with the p_clk. when these clocks are used, one of the clock outputs must be fed back to s_clkin. unused outputs may be disabled by: 1. writing the secondary clock disable bits in the configuration space 2. using the serial disable mask using the gpio pins and msk_in 3. terminating them electrically. 1.2.6 miscellaneous signals name pin # type description msk_in r21 i secondary clock disable serial input: this pin is used by bridge to disabl e secondary clock outputs. the serial stream is received by msk_in, starting when p_reset is detected deasserted and s_reset# is detected as being asserted. the serial data is used for selectively disabling secondary clock outputs and is shifted into the secondary clock control configuration register. this pin can be tied low to enable all secondary clock outputs or tied high to drive all the secondary clock outputs high. p_vio r20 i primary i/o voltage: this pin is used to determine either 3.3v or 5v signaling on the primary bus. p_vio must be tied to 3.3v only when all devices on the primary bus use 3.3v signaling. otherwise, p_vio is tied to 5v. s_vio n22 i secondary i/o voltage: this pin is used to determine either 3.3v or 5v signaling on the secondary bus. s_vio must be tied to 3.3v only when all devices on the secondary bus use 3.3v signaling. otherwise, s_vio is tied to 5v. bpcce r4 i bus/power clock control management pin: when this pin is tied high and the bridge is placed in the d2 or d3 hot power state, it enables the bridge to place the secondary bus in the b2 power state. the secondary clocks are disabled and driven to 0. when this pin is tied low, there is no effect on the secondary bus clocks when the bridge enters the d2 or d3 hot power state. config66 r22 i 66mhz configuration: this pin indicates if the bridge is capable of running at 66mhz operation. tie high to set bit [21] of offset 04h of the status register. pmeena# d11 i power management enable support: this pin sets bits [31:27] offset deh of the power management capabilities register. when tied low, bits [31:27] offset deh are set to 11111 to indicate that the secondary devices are capable of asserting pme#. when this pin is tied high, bits [31:27] offset deh are set to 00000 to indicate that pi7c8154a does not support the pme# pin. eedata a22 i/o eeprom data: serial data interface to the eeprom eeclk a23 o eeprom clock: clock signal to the eeprom interface used during th e autoload and vpd functions
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 19 of 112 july 2004 revision 1.00 ee_en# ac22 i eeprom enable: set to low to enable eeprom interface 1.2.7 general purpose i/o interface signals name pin # type description gpio[3:0] k2, k3 , l4, l1 ts general purpose i/o data pins: the 4 general- purpose signals are programmable as either input- only or bi-directional signals by writing the gpio output enable control register in the configuration space. 1.2.8 jtag boundary scan signals name pin # type description tck n20 i test clock. used to clock state information and data into and out of the bridge during boundary scan. tms p21 i test mode select. used to control the state of the test access port controller. tdo p22 o test data output. used as the serial output for the test instructions and data from the test logic. tdi p23 i test data input. serial input for the jtag instructions and test data. trst# n23 i test reset. active low signal to reset the test access port (tap) controller into an initialized state. 1.2.9 power and ground name pin # type description vdd a2, b1, b6, b20, b23, d5, d6, d10, d14, d15, d18, e22, h4, h20, j1, j3, j21, m4, m20, n4, r1, r23, t1, t4, t20, w3, y6, y10, y14, y18, y22, ab1, ab19, ab23, ac2, ac3, ac8, ac12, ac16 p power: +3.3v digital power. vss a1, a5, a12, a16, b2, b21, b22, c7, d8, d12, d16, d23, f4, f20, g23, h3, j2, k4, k20, l20, n2, p4, p20, t2, u21, v4, v20, y8, y9, y12, y16, aa2, aa22, ab2, ab22, ac1, ac4, ac13, ac17, ac20, ac23 p ground: digital ground. 1.3 pin list ball location pin name type ball location pin name type a1 vss p a2 vdd p a3 s_ad[30] ts a4 s_ad[27] ts a5 vss p a6 s_ad[23] ts
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 20 of 112 july 2004 revision 1.00 ball location pin name type ball location pin name type a7 s_ad[22] ts a8 s_ad[19] ts a9 s_ad[16] ts a10 s_trdy# sts a11 s_lock# sts a12 vss p a13 s_ad13] ts a14 sm66en i/od a15 s_cbe[0] ts a16 vss p a17 s_ad[2] ts a18 s_ad[0] ts a19 s_cbe[7] ts a20 s_cbe[5] ts a21 s_ad[62] ts a22 eedata i/o a23 eeclk o - - - b1 vdd p b2 vss p b3 s_ad[29] ts b4 s_ad[26] ts b5 s_ad[24] ts b6 vdd p b7 s_ad[20] ts b8 s_ad[18] ts b9 s_frame# sts b10 s_devsel# sts b11 s_serr# i b12 s_par ts b13 s_ad[14] ts b14 s_ad[10] ts b15 s_ad[8] ts b16 s_ad[6] ts b17 s_ad[4] ts b18 s_ad[1] ts b19 s_req64# sts b20 vdd p b21 vss p b22 vss p b23 vdd p - - - c1 s_req#[1] i c2 s_req#[2] i c3 s_ad[31] ts c4 s_ad[28] ts c5 s_ad[25] ts c6 s_cbe[3] ts c7 vss p c8 s_ad[17] ts c9 s_irdy# sts c10 s_stop# sts c11 s_perr# sts c12 s_cbe[1] ts c13 s_ad[15] ts c14 s_ad[11] ts c15 s_ad[9] ts c16 s_ad[7] ts c17 s_ad[5] ts c18 s_ack64# sts c19 s_cbe[6] ts c20 s_ad[63] ts c21 s_ad[60] ts c22 s_ad[58] ts c23 s_ad[59] ts - - - d1 s_req#[5] i d2 s_req#[6] i d3 s_req_[3] i d4 s_req#[0] i d5 vdd p d6 vdd p d7 s_ad[21] ts d8 vss p d9 s_cbe[2] ts d10 vdd p d11 pmeena# i d12 vss p d13 s_ad[12] ts d14 vdd p d15 vdd p d16 vss p d17 s_ad[3] ts d18 vdd p d19 s_cbe[4] ts d20 s_ad[61] ts d21 s_ad[57] ts d22 s_ad[55] ts d23 vss p - - - e1 s_req#[8] i e2 s_gnt#[0] ts e3 s_req#[7] i e4 s_req#[4] i - - - e20 s_ad[56] ts e21 s_ad[54] ts e22 vdd p e23 s_ad[53] ts - - - f1 s_gnt#[2] ts f2 s_gnt#[3] ts f3 s_gnt#[1] ts f4 vss p - - - f20 vss p f21 s_ad[52] ts f22 s_ad[50] ts f23 s_ad[51] ts - - - g1 s_gnt#[4] ts g2 s_gnt#[6] ts g3 s_gnt#[7] ts g4 s_gnt#[5] ts - - - g20 s_ad[49] ts g21 s_ad[47] ts g22 s_ad[48] ts g23 vss p - - - h1 s_gnt#[8] ts h2 s_reset# o h3 vss p h4 vdd p
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 21 of 112 july 2004 revision 1.00 ball location pin name type ball location pin name type - - - h20 vdd p h21 s_ad[44] ts h22 s_ad[45] ts h23 s_ad[46] ts - - - j1 vdd p j2 vss p j3 vdd p j4 s_clkin i - - - j20 s_ad[42] ts j21 vdd p j22 s_ad[41] ts j23 s_ad[43] ts - - - k1 s_cfn# i k2 gpio[3] ts k3 gpio[2] ts k4 vss p - - - k20 vss p k21 s_ad[38] ts k22 s_ad[39] ts k23 s_ad[40] ts - - - l1 gpio[0] ts l2 s_clkout[0] o l3 s_clkout[1] o l4 gpio[1] ts - - - l20 vss p l21 s_ad[36] ts l22 s_ad[35] ts l23 s_ad[37] ts - - - m1 s_clkout[3] o m2 s_clkout[4] o m3 s_clkout[2] o m4 vdd p - - - m20 vdd p m21 s_ad[32] ts m22 s_ad[34] ts m23 s_ad[33] ts - - - n1 s_clkout[6] o n2 vss p n3 s_clkout[5] o n4 vdd p - - - n20 tck i n21 s_par64 ts n22 s_vio i n23 trst# i - - - p1 s_clkout[9] o p2 s_clkout[8] o p3 s_clkout[7] o p4 vss p - - - p20 vss p p21 tms i p22 tdo o p23 tdi i - - - r1 vdd p r2 p_gnt# i r3 p_reset# i r4 bpcce i - - - r20 p_vio i r21 msk_in i r22 config66 i r23 vdd p - - - t1 vdd p t2 vss p t3 p_clk i t4 vdd p - - - t20 vdd p t21 p_par64 ts t22 p_ad[32] ts t23 p_ad[33] ts - - - u1 p_ad[29] ts u2 p_ad[31] ts u3 p_req# ts u4 p_ad[30] ts - - - u20 p_ad[35] ts u21 vss p u22 p_ad[34] ts u23 p_ad[36] ts - - - v1 p_ad[27] ts v2 p_ad[28] ts v3 p_ad[26] ts v4 vss p - - - v20 reserved 1 p v21 p_ad[39] ts v22 p_ad[37] ts v23 p_ad[38] ts - - - w1 p_ad[24] ts w2 p_ad[25] ts w3 vdd p w4 p_ad[23] ts - - - w20 p_ad[44] ts w21 p_ad[42] ts w22 p_ad[40] ts w23 p_ad[41] ts - - - y1 p_idsel i y2 p_cbe[3] ts 1 connected to ground
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 22 of 112 july 2004 revision 1.00 ball location pin name type ball location pin name type y3 p_ad[22] ts y4 p_ad[19] ts y5 p_ad[16] ts y6 vdd p y7 p_serr# od y8 vss p y9 vss p y10 vdd p y11 p_ad[8] ts y12 vss p y13 p_ad[1] ts y14 vdd p y15 p_cbe[5] ts y16 vss p y17 p_ad[59] ts y18 reserved 2 p y19 p_ad[52] ts y20 p_ad[47] ts y21 p_ad[45] ts y22 vdd p y23 p_ad[43] ts - - - aa1 p_ad[21] ts aa2 vss p aa3 p_ad[20] ts aa4 p_ad[17] ts aa5 p_frame# sts aa6 p_devsel# sts aa7 p_cbe[1] ts aa8 p_ad[14] ts aa9 p_ad[11] ts aa10 p_ad[9] ts aa11 p_ad[6] ts aa12 p_ad[5] ts aa13 p_ad[2] ts aa14 p_ad[0] ts aa15 p_cbe[7] ts aa16 p_ad[63] ts aa17 p_ad[61] ts aa18 p_ad[56] ts aa19 p_ad[54] ts aa20 p_ad[51] ts aa21 p_ad[48] ts aa22 vss p aa23 p_ad[46] ts - - - ab1 vdd p ab2 vss p ab3 p_ad[18] ts ab4 p_cbe[2] ts ab5 p_trdy# sts ab6 p_lock# i ab7 p_par ts ab8 p_ad[15] ts ab9 p_ad[12] ts ab10 p_m66en i ab11 p_ad[7] ts ab12 p_ad[4] ts ab13 p_ad[3] ts ab14 p_ack64# sts ab15 p_cbe[6] ts ab16 p_ad[62] ts ab17 p_ad[60] ts ab18 p_ad[58] ts ab19 vdd p ab20 p_ad[53] ts ab21 p_ad[50] ts ab22 vss p ab23 vdd p - - - ac1 vss p ac2 vdd p ac3 vdd p ac4 vss p ac5 p_irdy# sts ac6 p_stop# sts ac7 p_perr# sts ac8 vdd p ac9 p_ad[13] ts ac10 p_ad[10] ts ac11 p_cbe[0] ts ac12 vdd p ac13 vss p ac14 p_req64# sts ac15 p_cbe[4] ts ac16 vdd p ac17 vss p ac18 p_ad[57] ts ac19 p_ad[55] ts ac20 vss p ac21 p_ad[49] ts ac22 ee_en# i ac23 vss p - - - 2 signal definitions this chapter offers information about pci trans actions, transaction forwarding across pi7c8154a, and transaction termination. the pi7c8154a has two 128-byte buffers for read data buffering of upstream and downstream transactions. also, pi7c8154a has two 128-byte buffers for write data buffering of upstream and downstream transactions. 2 connected to v dd
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 23 of 112 july 2004 revision 1.00 2.1 types of transactions this section provides a summary of pci transactions performed by pi7c8154a. table 2-1 lists the command code and name of each pci transaction. the master and target columns indicate support for each transaction when pi7c8154a initiates tr ansactions as a master, on the primary and secondary buses, and when pi7c8154a responds to transactions as a target, on the primary and secondary buses. table 2-1 pci transactions types of transactions initiates as master responds as target primary secondary primary secondary 0000 interrupt acknowledge n n n n 0001 special cycle y y n n 0010 i/o read y y y y 0011 i/o write y y y y 0100 reserved n n n n 0101 reserved n n n n 0110 memory read y y y y 0111 memory write y y y y 1000 reserved n n n n 1001 reserved n n n n 1010 configuration read n y y n 1011 configuration write y (type 1 only) y y y (type 1 only) 1100 memory read multiple y y y y 1101 dual address cycle y y y y 1110 memory read line y y y y 1111 memory write and invalidate y y y y as indicated in table 2-1, the following pci commands are not supported by pi7c8154a: ! pi7c8154a never initiates a pci transaction with a reserved command code and, as a target, pi7c8154a ignores reserved command codes. ! pi7c8154a does not generate interrupt acknowledge transactions. pi7c8154a ignores interrupt acknowledge transactions as a target. ! pi7c8154a does not respond to special cycl e transactions. pi7c8154a cannot guarantee delivery of a special cycle transaction to downstr eam buses because of the broadcast nature of the special cycle command and the inability to control the transaction as a target. to generate special cycle transactions on other pci buses, either upstream or downstream, type 1 configuration write must be used. ! pi7c8154a neither generates type 0 configuration transactions on the primary pci bus nor responds to type 0 configuration transactions on the secondary pci bus. 2.2 single address phase a 32-bit address uses a single address phase. this address is driven on p_ad[31:0], and the bus command is driven on p_cbe[3:0]. pi7c8154a supports the linear increment address mode only, which is indicated when the lowest two address bits are equal to zero. if either of the lowest two address bits is nonzero, pi7c8 154a automatically disconnects the transaction after the first data transfer.
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 24 of 112 july 2004 revision 1.00 2.3 dual address phase a 64-bit address uses two address phases. the first address phase is denoted by the asserting edge of frame#. the second address phase alwa ys follows on the next clock cycle. for a 32-bit interface, the first address phase contains dual address command code on the cbe[3:0] lines, and the low 32 address bits on the ad[31:0] lines. the second address phase consists of the specific memory transaction command code on the cbe[3:0] lines, and the high 32 address bits on the ad[31:0] lines. in this way, 64-bit addre ssing can be supported on 32-bit pci buses. the pci-to-pci bridge architecture specification supports the use of dual address transactions in the prefetchable memory range only. see section 3.3.3 for a discussion of prefetchable address space. the pi7c8154a supports dual address transactions in both the upstream and the downstream direction. the pi7c8154a supports a programmable 64-bit address range in prefetchable memory for downstream forwarding of dual address trans actions. dual address transactions falling outside the prefetchable address range are forwarded upstream, but not downstream. prefetching and posting are performed in a manner consistent with the guidelines given in this document for each type of memory transaction in prefetchable memory space. 2.4 device select (dev sel#) generation pi7c8154a always performs positive address decoding (m edium decode) when accepting transactions on either the primary or secondary buses. pi7c8154a never does subtractive decode. 2.5 data phase the address phase of a pci transaction is followed by one or more data phases. a data phase is completed when irdy# and either trdy# or stop# ar e asserted. a transfer of data occurs only when both irdy# and trdy# are asserted during the same pci clock cycle. the last data phase of a transaction is indicated when frame# is de -asserted and both trdy# and irdy# are asserted, or when irdy# and stop# are asserted. see section 2.11 for further discussion of transaction termination. depending on the command type, pi7c8154a can support multiple data phase pci transactions. for detailed descriptions of how pi7c8154a imposes disconnect boundaries, see section 2.6.4 for write address boundaries and section 2.7.3 read address boundaries. 2.6 write transactions write transactions are treated as either posted write or delayed write transactions. table 2-2 shows the method of forwarding used for each type of write operation. table 2-2 write transaction forwarding type of transaction type of forwarding memory write posted (except vga memory) memory write and invalidate posted memory write to vga memory delayed i/o write delayed
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 25 of 112 july 2004 revision 1.00 type 1 configuration write delayed 2.6.1 memory write transactions posted write forwarding is used for ?memory write? and ?memory write and invalidate? transactions. when pi7c8154a determines that a memory write tr ansaction is to be forwarded across the bridge, pi7c8154a asserts devsel# with medium decode timing and trdy# in the next cycle, provided that enough buffer space is available in the posted memory write queue for the address and at least one dword of data. under this condition, pi7c 8154a accepts write data without obtaining access to the target bus. the pi7c8154a can accept one dword of write data every pci clock cycle. that is, no target wait state is inserted. th e write data is stored in an internal posted write buffers and is subsequently delivered to the targ et. the pi7c8154a continues to accept write data until one of the following events occurs: ! the initiator terminates the transactio n by de-asserting frame# and irdy#. ! an internal write address bounda ry is reached, such as a cach e line boundary or an aligned 4kb boundary, depending on the transaction type. ! the posted write data buffer fills up. when one of the last two events occurs, the pi7c8154a returns a target disconnect to the requesting initiator on this data phase to terminate the transaction. once the posted write data moves to the head of the posted data queue, pi7c8154a asserts its request on the target bu s. this can occur while pi7c8154a is still receiving data on the initiator bus. when the grant for the target bus is received and the target bus is detected in the idle condition, pi7c8154a asserts frame# and drives th e stored write address out on the target bus. on the following cycle, pi7c8154a drives the first dword of write data and continues to transfer write data until all write data corresponding to that transaction is delivered, or until a target termination is received. as long as write data exists in the queue, pi7c8154a can drive one dword of write data in each pci clock cycle; that is, no master wait states are inserted. if write data is flowing through pi7c8154a and the initiator stalls, pi7c8154a will signal the last data phase for the current transaction at the target bu s if the queue empties. pi7c8154a will restart the follow-on transactions if the queue has new data. pi7c8154a ends the transaction on the target bu s when one of the following conditions is met: ! all posted write data has been delivered to the target. ! the target returns a target disconnect or target retry (pi7c8154a starts another transaction to deliver the rest of the write data). ! the target returns a target abort (pi7c8154a discards remaining write data). ! the master latency timer expires, and pi7c8154a no longer has the target bus grant (pi7c8154a starts another transaction to deliver remaining write data). section 2.11.3.2 provides detailed information about how pi7c8154a responds to target termination during posted write transactions. 2.6.2 memory write and invalidate posted write forwarding is used for me mory write and invalidate transactions.
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 26 of 112 july 2004 revision 1.00 the pi7c8154a disconnects memory write and in validate commands at aligned cache line boundaries. the cache line size value in the cach e line size register gives the number of dword in a cache line. if the value in the cache line size register does meet the memory write and invalidate conditions, the pi7c8154a returns a target disconnect to the initiator on a cache line boundary. 2.6.3 delayed write transactions delayed write forwarding is used for i/o write transactions and type 1 configuration write transactions. a delayed write transaction guarantees that the act ual target response is returned back to the initiator without holding the initiating bus in wait stat es. a delayed write transaction is limited to a single dword data transfer. when a write transaction is first detected on the initiator bus, and pi7c8154a forwards it as a delayed transaction, pi7c8154a claims the access by asserting devs el# and returns a target retry to the initiator. during the address phase, pi 7c8154a samples the bus command, address, and address parity one cycle later. after irdy# is asserted, pi7c8154a also samples the first data dword, byte enable bits, and data parity. this information is placed into the delayed transaction queue. the transaction is queued only if no other existing delayed transactions have the same address and command, and if the delayed transac tion queue is not full. when the delayed write transaction moves to the head of the delayed tran saction queue and all ordering constraints with posted data are satisfied. the pi7c8154a initiates the transaction on the target bus. pi7c8154a transfers the write data to the ta rget. if pi7c8154a receives a target retry in response to the write transaction on the target bus, it continues to rep eat the write transaction un til the data transfer is completed, or until an error condition is encountered. if pi7c8154a is unable to deliver write data after 2 24 (default) or 2 32 (maximum) attempts, pi7c8154a will report a system error. pi7c8154a also asserts p_serr# if the primary serr# enable bit is set in the command register. see section 5.4 for information on the assertion of p_serr#. when the initiator repeats the same write transaction (same command, address, byte enable bits, and data), and the completed delayed transaction is at the head of the queue, the pi7c8154a claims the access by asserting devs el# and returns trdy# to the initiator, to indicate that the write data was transferred. if the initiator re quests multiple dword, pi7c8154a also asserts stop# in conjunction with trdy# to signal a target disconnect. note that only those bytes of write data with valid byte enable bits are compared. if any of the byte enable bits are turned off (driven high), the corresponding byte of write data is not compared. if the initiator repeats the write transaction before the data has been transferred to the target, pi7c8154a returns a target retry to the initiator. pi7c8154a continues to return a target retry to the initiator until write data is delivered to the ta rget, or until an error condition is encountered. when the write transaction is re peated, pi7c8154a does not make a new entry into the delayed transaction queue. section 2.11.3.1 provides de tailed information about how pi7c8154a responds to target termination during delayed write transactions. pi7c8154a implements a discard ti mer that starts counting when the delayed write completion is at the head of the delayed transaction completion queu e. the initial value of this timer can be set to the retry counter register offset 78h.
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 27 of 112 july 2004 revision 1.00 if the initiator does not repeat the delayed write transaction before the discard timer expires, pi7c8154a discards the delayed write completion from the delayed transaction completion queue. pi7c8154a also conditionally asserts p_serr# (see section 5.4). 2.6.4 write transaction address boundaries pi7c8154a imposes internal address boundaries wh en accepting write data. the aligned address boundaries are used to prevent pi7c8154a from continuing a transaction over a device address boundary and to provide an upper limit on maximum latency. pi7c78154 returns a target disconnect to the initiator when it reaches the aligned address boundaries under conditions shown in table 2-3. table 2-3 write transaction disconnect address boundaries type of transaction conditi on aligned address boundary delayed write all disconnects after one data transfer posted memory write memory write disconnect control bit = 0 (1) 4kb aligned address boundary posted memory write memory write disconnect control bit = 1 (1) disconnects at cache line boundary posted memory write and invalidate cache line size 1, 2, 4, 8, 16 4kb aligned address boundary posted memory write and invalidate cache line size = 1, 2, 4, 8 cache line boundary if posted memory write data fifo does not have enough space for the next cache line posted memory write and invalidate cache line size = 16 16-dword aligned address boundary note 1. memory write disconnect control bit is bit 1 of the chip control register at offset 40h in the configuration space. 2.6.5 buffering multiple write transactions pi7c8154a continues to accept posted memory write transactions as long as space for at least one dword of data in the posted write data buffer rema ins. if the posted write data buffer fills before the initiator terminates the write transaction, pi7c81 54a returns a target disconnect to the initiator. delayed write transactions are accepted as long as at least one open entry in the delayed transaction queue exists. therefore, several posted and delayed write transactions can exist in data buffers at the same time. see chapter 4 for information about how multiple posted and delayed write transactions are ordered. 2.6.6 fast back-to-back transactions pi7c8154a is capable of decoding and forwarding fast back-to-back write transactions. when pi7c8154a cannot accept the second transaction because of buffer space limitations, it returns a target retry to the initiator. the fast back-to-back enable bit must be set in the command register for upstream write transactions, and in the bridge cont rol register for downstre am write transactions. 2.7 read transactions
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 28 of 112 july 2004 revision 1.00 delayed read forwarding is used for all read transactions crossing pi7c8154a. delayed read transactions are treated as eith er prefetchable or non-prefetch able. table 2-5 shows the read behavior, prefetchable or non-prefetchabl e, for each type of read operation. 2.7.1 prefetchable read transactions a prefetchable read transaction is a read tr ansaction where pi7c8154a performs speculative dword reads, transferring data from the target before it is requested from the initiator. this behavior allows a prefetchable read transaction to consist of multiple data transfers. however, byte enable bits cannot be forwarded for all data phases as is done for the single data phase of the non- prefetchable read transaction. fo r prefetchable read transactions, pi7c8154a forces all byte enable bits to be on for all data phases. prefetchable behavior is used for memory read line and memory read multiple transactions, as well as for memory read transactions that fall into prefetchable memory space. the amount of data that is prefetched depends on the type of transaction. the amount of prefetching may also be affected by the amount of free buffer space available in pi7c8154a, and by any read address boundaries encountered. prefetching should not be used for those read transactions that have side effects in the target device, that is, control and status registers, fifo?s, and so on. the target device?s base address register or registers indicate if a memory address region is prefetchable. 2.7.2 non-prefetchable read transactions a non-prefetchable read transaction is a read transaction where pi7c8154a requests one and only one dword from the target and disconnects the initiator after delivery of the first dword of read data. unlike prefetchable read transactions, pi7c8154a forwards the read byte enable information for the data phase. non-prefetchable behavior is used for i/o and configuration read transactions, as well as for memory read transactions that fall into non-prefetchable memory space. if extra read transactions could have side eff ects, for example, when accessing a fifo, use non- prefetchable read transactions to those locations. ac cordingly, if it is important to retain the value of the byte enable bits during the data phase, use non-prefetchable read transactions. if these locations are mapped in memory space, use the memory read command and map the target into non-prefetchable (memory-mapped i/o) memo ry space to use non-prefetching behavior. 2.7.3 read prefetch address boundaries pi7c8154a imposes internal read address boundaries on read prefetched data. when a read transaction reaches one of these aligned address boundaries, the pi7c8154a stops pre-fetched data, unless the target signals a target disconnect before the read prefetched bou ndary is reached. when pi7c8154a finishes transferring this read data to the initiator, it returns a target disconnect with the last data transfer, unless the initiator completes the transaction before all pre-fetched read data is delivered. any leftover pre-fetched data is discarded.
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 29 of 112 july 2004 revision 1.00 prefetchable read transactions in flow-through mode pre-fetch to the nearest aligned 4kb address boundary, or until the initiator de-asserts frame# . section 2.7.6 describes flow-through mode during read operations. table 2-4 shows the read pre-fetch address boundaries for read transactions during non-flow- through mode. table 2-4 read prefetch address boundaries type of transaction address space cache line size (cls) prefetch aligned address boundary configuration read - * one dword (no prefetch) i/o read - * one dword (no prefetch) memory read non-prefetchable * one dword (no prefetch) memory read prefetchable cls = 0 or 16 16-dword aligned address boundary memory read prefetchable cls = 1, 2, 4, 8 cache line address boundary memory read line - cls = 0 or 16 16-dword aligned address boundary memory read line - cls = 1, 2, 4, 8 cache line boundary memory read multiple - cls = 0 or 16 queue full memory read multiple - cls = 1, 2, 4, 8 second cache line boundary - does not matter if it is pref etchable or non-prefetchable * don?t care table 2-5 read transaction prefetching type of transaction read behavior i/o read prefetching never allowed configuration read prefetching never allowed downstream: prefetching used if address is prefetchable space memory read upstream: prefetching used or programmable memory read line prefetching always used memory read multiple prefetching always used see section 3.3 for detailed info rmation about prefetchable and non-prefetchable address spaces. 2.7.4 delayed read requests pi7c8154a treats all read trans actions as delayed read transactions, which means that the read request from the initiator is posted into a delayed tr ansaction queue. read data from the target is placed in the read data queue directed toward th e initiator bus interface an d is transferred to the initiator when the initiator repeats the read transaction. pi7c8154a accepts a delayed read request, by samp ling the read address, read bus command, and address parity. when irdy# is asserted, pi7c8154a then samples the byte enable bits for the first data phase. this information is entered into th e delayed transaction queu e. pi7c8154a terminates the transaction by signaling a target retry to the initiator. upon reception of the target retry, the initiator is required to continue to repeat the same read transaction until at least one data transfer is completed, or until a target response (target abort or master abort) other than a target retry is received. 2.7.5 delayed read completion on target bus when delayed read request reaches the head of the delayed transaction queue, pi7c8154a arbitrates for the target bus and initiates the read transaction only if all previously queued posted write transactions have been delivered. pi7c8154a uses the exact read address and read command
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 30 of 112 july 2004 revision 1.00 captured from the initiator during the initial delayed r ead request to initiate the read transaction. if the read transaction is a non-prefetchable read, pi 7c8154a drives the captured byte enable bits during the next cycle. if the tran saction is a prefetchable read transaction, it drives all byte enable bits to zero for all data phas es. if pi7c8154a receives a target retry in response to the read transaction on the target bus, it continues to re peat the read transaction until at least one data transfer is completed, or until an error condition is encountered. if the transaction is terminated via normal master termination or target disconnect afte r at least one data transfer has been completed, pi7c8154a does not initiate any further attempts to read more data. if pi7c8154a is unable to obtain read data from the target after 2 24 (default) or 2 32 (maximum) attempts, pi7c8154a will report system error. the number of attempts is programmable. pi7c8154a also asserts p_serr# if the primary serr# enable bit is set in the command register. see section 5.4 for information on the assertion of p_serr#. once pi7c8154a receives devsel# and trdy# from the target, it transfers the data read to the opposite direction read data queue, pointing toward the opposite inter-face, before terminating the transaction. for example, read data in response to a downstream read transaction initiated on the primary bus is placed in the upstream read da ta queue. the pi7c8154a can accept one dword of read data each pci clock cycle; that is, no ma ster wait states are inserted. the number of dword?s transferred during a delayed read tran saction matches the prefetch address boundary given in table 2-4 (assum ing no disconnect is r eceived from the target). 2.7.6 delayed read completion on initiator bus when the transaction has been completed on the target bus, and the delayed read data is at the head of the read data queue, and all ordering constraints with posted write transactions have been satisfied, the pi7c8154a transfers the data to the initiator when the initiator repeats the transaction. for memory read transactions, pi7c8154a aliases memory read line and memory read multiple bus commands to memory read when matching the bus command of the transaction to the bus command in the delayed transaction queue if bit[3] of offset 74h is set to ?1?. pi7c8154a returns a target disconnect along with the transfer of the last dword of read data to the initiator. if pi7c8154a initiator terminates the transaction be fore all read data has been transferred, the remaining read data left in data buffers is discarded. when the master repeats the transaction and starts transferring prefetchable read data from data buffers while the read transaction on the target bus is still in progress and before a read boundary is reached on the target bus, the read transaction starts operating in flow-through mode. because data is flowing through the data buffers from the target to the initiator, long read bursts can then be sustained. in this case, the read transaction is allowed to continue until the initiator terminates the transaction, or until an aligned 4kb address bounda ry is reached, or until the buffer fills, whichever comes first. when the buffer em pties, pi7c8154a reflects the stalled condition to the initiator by disconnecting the initiator with data. the initiator may retry the transaction later if data are needed. if the initiator does not need any more data, the initiator will not continue the disconnected transaction. in this case, pi7c 8154a will start the master timeout timer. the remaining read data will be discarded after the master timeout timer expi res. to provide better latency, if there are any other pending data for other transactions in the rdb (read data buffer), the remaining read data will be discarded even though the master timeout timer has not expired. pi7c8154a implements a master timeout timer that starts counting when the delayed read completion is at the head of the delayed transaction queue, and the read data is at the head of the read data queue. the initial value of this timer is programmable through configuration transaction. if the initiator does not repeat the read transaction and before the master timeout timer expires (2 15
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 31 of 112 july 2004 revision 1.00 default), pi7c8154a discards the read transaction and read data from its queues. pi7c8154a also conditionally asserts p_serr# (see section 5.4). pi7c8154a has the capability to post multiple delayed read requests, up to a maximum of four in each direction. if an initiator starts a read tran saction that matches the address and read command of a read transaction that is already queued, the cu rrent read command is not posted as it is already contained in the delayed transaction queue. see section 4 for a discussion of how delayed read transactions are ordered when crossing pi7c8154a. 2.7.7 fast back-to-back transactions pi7c8154a is capable of decoding fast back-to-back read transactions on both the primary and secondary. also, pi7c8154a cannot generate fast back-to-back read transactions on the secondary or primary even though bit[23] of offset 3ch is se t to ?1? or bit[9] of offset 04h is set to ?1?. 2.8 configuration transactions configuration transactions are used to initialize a pci system. every pci device has a configuration space that is accessed by configur ation commands. all registers are accessible in configuration space only. in addition to accepting co nfiguration transactions for initializa tion of its own configuration space, the pi7c8154a also forwards configuration trans actions for device initialization in hierarchical pci systems, as well as for special cycle generation. to support hierarchical pci bus systems, two type s of configuration trans actions are specified: type 0 and type 1. type 0 configuration transactions are issued when the intended targ et resides on the same pci bus as the initiator. a type 0 configuration transacti on is identified by the configuration command and the lowest two bits of the address set to 00b. type 1 configuration transactions are issued when the intended target resides on another pci bus, or when a special cycle is to be generated on another pci bus. a type 1 configuration command is identified by the configuration command and the lowest two address bits set to 01b. the register number is found in both type 0 and type 1 formats and gives the dword address of the configuration register to be accessed. the func tion number is also included in both type 0 and type 1 formats and indicates which function of a multifunction device is to be accessed. for single-function devices, this value is not decoded. the addresses of type 1 configuration transaction include a 5-bit field designating the device number that identifies the device on the target pci bus that is to be accessed. in addition, the bus number in type 1 transactions specifies the pci bus to which the transaction is targeted. 2.8.1 type 0 access to pi7c8154a
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 32 of 112 july 2004 revision 1.00 the configuration space is accessed by a type 0 co nfiguration transaction on the primary interface. the configuration space cannot be accessed from th e secondary bus. the pi 7c8154a responds to a type 0 configuration transactio n by asserting p_devsel# when the following conditions are met during the address phase: ! the bus command is a configuration read or configuration write transaction. ! lowest two address bits p_ad[1:0] must be 00b. ! signal p_idsel must be asserted. pi7c8154a limits all configuration access to a si ngle dword data transfer and returns target- disconnect with the first data transfer if addi tional data phases are requested. because read transactions to configuration space do not have si de effects, all bytes in the requested dword are returned, regardless of the value of the byte enable bits. type 0 configuration write and read transactions do not use data buffers; that is, these transactions are completed immediately, regardless of the stat e of the data buffers. the pi7c8154a ignores all type 0 transactions initiated on the secondary interface. 2.8.2 type 1 to type 0 configuration type 1 configuration transactions are used specifi cally for device configura tion in a hierarchical pci bus system. a pci-to-pci bridge is the only type of device that should respond to a type 1 configuration command. type 1 configuration comma nds are used when the configuration access is intended for a pci device that resides on a pci bus other than the one where the type 1 transaction is generated. pi7c8154a performs a type 1 to type 0 translation when the type 1 transaction is generated on the primary bus and is intended for a device att ached directly to the se condary bus. pi7c8154a must convert the configuration command to a type 0 format so that the secondary bus device can respond to it. type 1 to type 0 translations are pe rformed only in the downstream direction; that is, pi7c8154a generates a type 0 transaction only on the secondary bus, and never on the primary bus. pi7c8154a responds to a type 1 configuration transaction and translates it into a type 0 transaction on the secondary bus when the following conditions ar e met during the address phase: ! the lowest two address bits on p_ad[1:0] are 01b. ! the bus number in address field p_ad[23:16] is equal to the value in the secondary bus number register in configuration space. ! the bus command on p_cbe[3:0] is a configuration read or configuration write transaction. when pi7c8154a translates the type 1 transaction to a type 0 transaction on the secondary interface, it performs the following translations to the address: ! sets the lowest two address bits on s_ad[1:0] to 0. ! decodes the device number and drives the bit pa ttern specified in table 2-6 on s_ad[31:16] for the purpose of asserting the device?s idsel signal. ! sets s_ad[15:11] to 0. ! leaves unchanged the function number and register number fields. pi7c8154a asserts a unique address line based on the device number. these address lines may be used as secondary bus idsel signals. the mapping of the address lines depends on the device
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 33 of 112 july 2004 revision 1.00 number in the type 1 address bits p_ad[15:11]. table 2-6 presents the mapping that pi7c8154a uses. table 2-6 device number to idsel s_ad pin mapping device number p_ad[15:11] secondary idsel s_ad[31:16] s_ad 0h 00000 0000 0000 0000 0001 16 1h 00001 0000 0000 0000 0010 17 2h 00010 0000 0000 0000 0100 18 3h 00011 0000 0000 0000 1000 19 4h 00100 0000 0000 0001 0000 20 5h 00101 0000 0000 0010 0000 21 6h 00110 0000 0000 0100 0000 22 7h 00111 0000 0000 1000 0000 23 8h 01000 0000 0001 0000 0000 24 9h 01001 0000 0010 0000 0000 25 ah 01010 0000 0100 0000 0000 26 bh 01011 0000 1000 0000 0000 27 ch 01100 0001 0000 0000 0000 28 dh 01101 0010 0000 0000 0000 29 eh 01110 0100 0000 0000 0000 30 fh 01111 1000 0000 0000 0000 31 10h ? 1eh 10000 ? 11110 0000 0000 0000 0000 - 1fh 11111 generate special cycle (p_ad[7:2] = 00h) 0000 0000 0000 0000 (p_ad[7:2] = 00h) - pi7c8154a can assert up to 16 unique address lines to be used as idsel signals for up to 16 devices on the secondary bus, for device numbers ranging from 0 through 8. because of electrical loading constraints of the pci bus, more than 16 idsel signals should not be necessary. however, if device numbers greater than 16 are desired, some external method of generating idsel lines must be used, and no upper address bits are then asserted. the configuration transaction is still translated and passed from the primary bus to the secondary bus. if no idsel pin is asserted to a secondary device, the transaction ends in a master abort. pi7c8154a forwards type 1 to type 0 configuration read or write transactions as delayed transactions. type 1 to type 0 configuration read or write transactions are limited to a single 32-bit data transfer. 2.8.3 type 1 to type 1 forwarding type 1 to type 1 transaction forwarding provid es a hierarchical configuration mechanism when two or more levels of pci-to-pci bridges are used. when pi7c8154a detects a type 1 configuration transaction intended for a pci bus downstream from the secondary bus, pi7c8154a forwards the transaction unchanged to the secondary bus. ultimately, this transaction is translated to a ty pe 0 configuration command or to a special cycle transaction by a downstream pci-to-pci bridge. downstream type 1 to type 1 forwarding occurs when the following conditions are met during the address phase: ! the lowest two address bits are equal to 01b. ! the bus number falls in the range defined by the lower limit (exclusive) in the secondary bus number register and the upper limit (inclusive) in the subordinate bus number register. ! the bus command is a configuratio n read or write transaction.
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 34 of 112 july 2004 revision 1.00 pi7c8154a also supports type 1 to type 1 forwarding of configuration write transactions upstream to support upstream special cycle ge neration. a type 1 configuration command is forwarded upstream when the following conditions are met: ! the lowest two address bits are equal to 01b. ! the bus number falls outside the range defined by the lower limit (inclusive) in the secondary bus number register and the upper limit (inclusive) in the subordinate bus number register. ! the device number in address bits ad[15:11] is equal to 11111b. ! the function number in address bits ad[10:8] is equal to 111b. ! the bus command is a configuration write transaction. the pi7c8154a forwards type 1 to type 1 configuration write transactions as delayed transactions. types 1 to type 1 configuration write transactions are limited to a single data transfer. 2.8.4 special cycles the type 1 configuration mechanism is used to gene rate special cycle transactions in hierarchical pci systems. special cycle transactions are ignor ed by acting as a target and are not forwarded across the bridge. special cycle transactions can be generated from type 1 configuration write transactions in either the upstream or the down-stream direction. pi7c8154a initiates a special cycle on the target bu s when a type 1 configuration write transaction is being detected on the initiating bus and the following conditions are met during the address phase: ! the lowest two address bits on ad[1:0] are equal to 01b. ! the device number in address bits ad[15:11] is equal to 11111b. ! the function number in address bits ad[10:8] is equal to 111b. ! the register number in address bits ad[7:2] is equal to 000000b. ! the bus number is equal to the value in the secondary bus number register in configuration space for downstream forwarding or equal to the value in the primary bus number register in configuration space for upstream forwarding. ! the bus command on cbe is a configuration write command. when pi7c8154a initiates the transaction on the target interface, the bus command is changed from configuration write to special cycle. the address and data ar e for-warded unchanged. devices that use special cycles ignore the address and decode only the bus command. the data phase contains the special cycle message. the transacti on is forwarded as a delayed transaction, but in this case the target response is not forwarded back (because special cycles result in a master abort). once the transaction is completed on the target bus, through detection of the master abort condition, pi7c8154a responds with trdy# to the next attempt of the con-figuration transaction from the initiator. if more than one data transfer is requested, pi7c8154a responds with a target disconnect operation during the first data phase. 2.9 64-bit operation both the primary and secondary interfaces of the pi7c8154a support 32 -bit operation and 64-bit operation. this chapter describes how to use the 64-bit operations as well as the conditions that go along with it.
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 35 of 112 july 2004 revision 1.00 2.9.1 64-bit and 32-bit transactio ns initiated by pi7c8154a 64-bit transactions are requested by asserting p_req64# on the primary and s_req64# on the secondary during the address phase. req64# is asse rted and deasserted duri ng the same cycles as frame#. under certain conditions, pi7c8154a does not use the 64-bit extension when initiating transactions. in this case, req64# is not asserted. if req64# is not asserted, the transaction is in itiated as a 32-bit transaction when any of the following conditions are met: ! p_req64# was not asserted by the primary during reset (64-bit extension not supported on the primary) for upstream transactions only ! pi7c8154a is initiating an i/o transaction ! pi7c8154a is initiating a special cycle transaction ! pi7c8154a is initiating a co nfiguration transaction ! pi7c8154a is initiating a nonprefetc hable memory read transaction ! the address is not quadword aligned ! the address is near th e top of a cache line ! a single dword read transaction is being performed ! a single or two-dword memory write transaction is being performed ! pi7c8154a is resuming memory write transacti on after a target disconnect, and ack64# was not asserted by the target in the previous transaction ? does not apply when the previous target termination was a target retry 2.9.2 64-bit transactions ? address phase when a transaction using the primary bus 64-bit exte nsion is a single address cycle, the upper 32- bits of the address, ad[63:32], are assumed to be 0 and cbe[7:4] are not defined but driven to valid logic levels during the address phase. when a transaction using the primary bus 64-bit ex tension is a dual address cycle, the upper 32-bit of the address, ad[63:32], contain the upper 32-b its of the address and cbe[7:4] contain memory bus command during both address phases. a 64-bit target then has the opportunity to decode the entire 64-bit address and bus command after the firs t address phase. a 32-bit target needs both address phases to decode th e full address and bus command. 2.9.3 64-bit transactions ? data phase pi7c8154a asserts req64# to indicate it is in itiating a 64-bit transfer during memory write transactions. during the data phas e, pi7c8154a asserts the following: ! the low 32 bits of data on ad[31:0] ! the low 4 bits on cbe[3:0] ! the high 32 bits of data on ad[63:32] ! the high 4 bits on cbe[7:4] every data phase will consist of 64 bits and 8 by te enable bits when pi7c8154a detects ack64## asserted by the target at the same time it detects devsel#.
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 36 of 112 july 2004 revision 1.00 for write transactions, pi7c8154a redirects the wr ite data that it has on the ad[63:32] bus to ad[31:0] during the second data phase if it does not detect ack64# asserted at the same time that it detects devsel# asserted. also, the cbe[7:4] is redirected to cbe[3:0] during the second data phase. for 64-bit memory write transactions that end at an odd dword boundary, pi7c8154a drives the byte enable bits to 1 during the last data phase. ad[63:32] are then unpredictable but are driven to a valid logic level. for read transactions, pi7c8154a drives 8 bits of byte enables on cbe[7:0] when it has asserted req64#. cbe[7:0] is always 0 because the only re ad transactions that use the 64-bit extension are prefetchable memory reads. no special redirection is needed based on the target?s assertion or lack of assertion of ack64#. when the target asserts ack64# at the same time that it asserts devsel#, all read data transfers consist of 64 bits and the target asserts par64, which covers ad[63:32] and cbe[7:4]. all data phase consist of 32-bit transactions when the target does not assert ack64# and asserts devsel#. 2.9.4 64-bit transactions ? re ceived by pi7c8154a pi7c8154a does one of 2 things when it is the ta rget of a transaction an d req64# is asserted. pi7c8154a either asserts ack64# at the same ti me it asserts devsel# to indicate its ability to perform 64-bit data transfers, or it does not use th e 64-bit extension as a target and does not assert ack64#. pi7c8154a does not assert ack64# under any of the following conditions: ! req64# was not asserted by the initiator ! pi7c8154a is responding to a non-prefetchable memory read transaction ! pi7c8154a is responding to an i/o transaction ! pi7c8154a is responding to a configuration transaction ! only 1 dword of data was read from the target if pi7c8154a is the target of a 64 -bit memory write transaction, it is able to accept 64 bits of data during each data phase. if pi7c8154a is the target of a memory read transaction, it delivers 64 bits of read data during each data phase and drives par64 corresponding to ad[63:32] and cbe[7:4] for each data phase. if an odd number of dwor ds is read from the target and pi7c8154a has asserted ack64# when returning read data to the initiator, pi7c8154a disconnects before the last dword is returned. pi7c8154a may have read an odd number of dword?s because of either a target disconnect or a master latency timer expira tion during 32-bit data transfers on the opposite interface. 2.9.5 64-bit transactions ? support during reset pi7c8154a checks p_req64# while p_reset# is asserted to determine whether the 64-bit extensions are connected. if p_req64# is high, pi7c8154a knows that the 64-bit extension signals are not connected so it always drives the 64-bit extension outputs to have valid logic levels on the inputs. pi7c8154a will then treat all transactions on the prim ary as 32-bit. if p_req64# is low, the 64-bit signals should be connected to pull-up resistors on the board and pi7c8154a does not perform any input biasing. pi7c8154a can then treat memory write and prefetchable memory read transactions as 64-bit tr ansactions on the primary.
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 37 of 112 july 2004 revision 1.00 pi7c8154a always asserts s_req64# low duri ng s_reset# to indicate that the 64-bit extension is supported on the secondary bus. individual pull-up resistors must always be supplied for s_ad[63:32], s_cbe[7:4], and s_par64. 2.10 transaction flow through transaction flow through refers to data being removed from the read/write buffers concurrently as data is still being written to the buffer. for reads, flow through occurs when the initiator repeats the delayed transaction while some read data is in the buffer, but the transaction is still ongoing on the target bus. for read flow through to occur, there can be no other reads or writes previously posted in the same direction. for writes, flow through occurs wh en pi7c8154a is able to arbitrate for the target bus, initiate the transaction and receive trdy# from the target, wh ile receiving data from the same transaction on the initiator bus. flow through can only occur if the writes that were previously posted in the same direction are completed. 2.11 transaction termination this section describes how pi7c8154a returns tr ansaction termination conditions back to the initiator. the initiator can terminate transactions with one of the following types of termination: ! normal termination normal termination occurs when the initiator de-asse rts frame# at the beginning of the last data phase, and de-asserts irdyl at the end of the last data phase in conjunction with either trdy# or stop# assertion from the target. ! master abort a master abort occurs when no target response is detected. when the initiator does not detect a devsel# from the target within five clock cycles after asserting frame#, the initiator terminates the transaction with a master ab ort. if frame# is still asserted, the initiator de-asserts frame# on the next cycle, and then de-asserts irdy# on the following cycle. irdy# must be asserted in the same cycle in which frame# deasserts. if frame# is already deasserted, irdy# can be deasserted on the next clock cycle following detection of the master abort condition. the target can terminate trans actions with one of the following types of termination: ! normal termination trdy# and devsel# asserted in conjunction w ith frame# deasserted and irdy# asserted. ! target retry stop# and devsel# asserted with trdy# deasserted during the first data phase. no data transfers occur during the transaction. this transaction must be repeated. ! target disconnect with data transfer stop#, devsel# and trdy# asserted. it signals th at this is the last data transfer of the transaction.
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 38 of 112 july 2004 revision 1.00 ! target disconnect wi thout data transfer stop# and devsel# asserted with trdy# de-asserted after previous data transfers have been made, indicating that no more data transfer s will be made during this transaction. ! target abort stop# asserted with devsel# and trdy# de-asserted. indicates that target will never be able to complete this transaction. devsel# must be assert ed for at least one cycle during the transaction before the target abort is signaled. 2.11.1 master termination in itiated by pi7c8154a pi7c8154a, as an initiator, uses normal termination if devsel# is returned by target within five clock cycles of pi7c8154a?s assertion of frame# on the target bus. as an initiator, pi7c8154a terminates a transaction when the following conditions are met: ! during a delayed write transacti on, a single dword is delivered. ! during a non-prefetchable read transaction, a single dword is transferred from the target. ! during a prefetchable read transactio n, a pre-fetch boundary is reached. ! for a posted write transaction, all write data for the transaction is transf erred from data buffers to the target. ! for burst transfer, with the exception of ?memory write and invalidate? transactions, the master latency timer expires and the pi7c8154a?s bus grant is de-asserted. ! the target terminates the transaction with a retry, disconnect, or target abort. if pi7c8154a is delivering posted write data when it terminates the transaction because the master latency timer expires, it initiates another trans action to deliver the remaining write data. the address of the transaction is updated to reflect the address of the current dword to be delivered. if pi7c8154a is pre-fetching read data when it terminates the transaction because the master latency timer expires, it does not repeat the transaction to obtain more data. 2.11.2 master abort receiv ed by pi7c8154a if the initiator initiates a transaction on the target bus and does not detect devsel# returned by the target within five clock cycles of the assertion of frame#, pi7c8154a terminates the transaction with a master abort. this sets the received-master-abo rt bit in the status register corresponding to the target bus. for delayed read and write transactions, pi7c8154 a is able to reflect the master abort condition back to the initiator. when pi7c8154a detects a mast er abort in response to a delayed transaction, and when the initiator repeats the transaction, pi7c 8154a does not respond to the transaction with devsel#, which induces the master abort condition back to the initiator. the transaction is then removed from the delayed transaction queue. when a master abort is received in response to a posted write transaction, pi7c8154a discards the pos ted write data and makes no more attempts to deliver the data. pi7c8154a sets the received-master-abort bit in the status register when the master abort is received on the pr imary bus, or it sets the received master abort bit in the secondary status register when the master abort is received on the secondary interface. when master abort is detected in posted write transaction with both master-abort-mode bit (bit[5] of bridge control register) and the serr# enable bit (bit 8 of command register for secondary bus) are set,
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 39 of 112 july 2004 revision 1.00 pi7c8154a asserts p_serr# if the master-abort-o n-posted-write is not set. the master-abort-on- posted-write bit is bit 4 of the p_serr# event disable register (offset 64h). note: when pi7c8154a performs a type 1 to special cycle conversion, a master abort is the expected termination for the special cycle on the target bus. in this case, the master abort received bit is not set, and the type 1 configuration trans action is disconnected after the first data phase. 2.11.3 target termination re ceived by pi7c8154a when pi7c8154a initiates a transaction on the targ et bus and the target responds with devsel#, the target can end the transaction with one of the following types of termination: ! normal termination (upon de-assertion of frame#) ! target retry ! target disconnect ! target abort pi7c8154a handles these terminations in different ways, depending on the type of transaction being performed. 2.11.3.1 delayed write target ter mination response when pi7c8154a initiates a delayed write transaction, the type of target termination received from the target can be passed back to the initiator.
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 40 of 112 july 2004 revision 1.00 table 2-7 shows the response to each type of target termination that occurs during a delayed write transaction. pi7c8154a repeats a delayed write transaction until one of the following conditions is met: ! pi7c8154a completes at least one data transfer. ! pi7c8154a receives a master abort. ! pi7c8154a receives a target abort. pi7c8154a makes 2 24 (default) or 2 32 (maximum) write attempts resulting in a response of target retry.
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 41 of 112 july 2004 revision 1.00 table 2-7 delayed write target termination response target termination response normal returning disconnect to initiator with first data transf er only if multiple data phases requested. target retry returning target retry to initiator. continue write attempts to target target disconnect returning disconn ect to initiator with first data tr ansfer only if multiple data phases requested. target abort returning target abort to initiator. set receiv ed target abort bit in target interface status register. set signaled target abort bit in initiator interface status register. after the pi7c8154a makes 2 24 (default) attempts of the same delayed write trans-action on the target bus, pi7c8154a asserts p_serr# if the serr# enable bit (bit 8 of command register for the secondary bus) is set and the delayed-write-non -delivery bit is not set. the delayed-write-non- delivery bit is bit 5 of p_serr# event disable re gister (offset 64h). pi7c 8154a will report system error. see section 5.4 for a description of system error conditions. 2.11.3.2 posted write target termination response when pi7c8154a initiates a posted write transaction, the target termination cannot be passed back to the initiator. table 2-8 shows the response to each type of target termination that occurs during a posted write transaction. table 2-8 response to po sted write target termination target termination repsonse normal no additional action. target retry repeating write transaction to target. target disconnect initiate write transaction for delivering remaining posted write data. target abort set received-target-abort bit in the ta rget interface status register. assert p_serr# if enabled, and set the signaled-system-e rror bit in primary status register. note that when a target retry or target disconnect is returned and po sted write data associated with that transaction remains in the write buffers, pi7c81 54a initiates another write transaction to attempt to deliver the rest of the write data. if ther e is a target retry, the exact same address will be driven as for the initial write trans-action attempt. if a target disconnect is received, the address that is driven on a subsequent write transaction atte mpt will be updated to reflect the address of the current dword. if the initial wr ite transaction is memory-write-a nd-invalidate transaction, and a partial delivery of write data to the target is performed before a target disconnect is received, pi7c8154a will use the memory write command to deli ver the rest of the write data. it is because an incomplete cache line will be transferred in the subsequent write transaction attempt. after the pi7c8154a makes 2 24 (default) write trans action attempts and fails to deliver all posted write data associated with that transaction, pi7c8154a asserts p_serr# if the primary serr# enable bit is set (bit 8 of command register for s econdary bus) and posted-write-non-delivery bit is not set. the posted-write-non-deliv ery bit is the bit 2 of p_serr# event disable register (offset 64h). pi7c8154a will report system error. see s ection 5.4 for a discussion of system error conditions. 2.11.3.3 delayed read target termination response when pi7c8154a initiates a delayed read transactio n, the abnormal target responses can be passed back to the initiator. other target responses depend on how much data the initiator requests. table
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 42 of 112 july 2004 revision 1.00 2-9 shows the response to each type of target termination that occurs during a delayed read transaction. pi7c8154a repeats a delayed read transaction until one of the following conditions is met: ! pi7c8154a completes at least one data transfer. ! pi7c8154a receives a master abort. ! pi7c8154a receives a target abort. pi7c8154a makes 2 24 (default) read attempts resulting in a response of target retry. table 2-9 response to delayed read target termination target termination response normal if prefetchable, target disconnect onl y if initiator requests mo re data than read from target. if non-prefetchable, ta rget disconnect on first data phase. target retry re-initiate r ead transaction to target target disconnect if initiator request s more data than read from targ et, return target disconnect to initiator. target abort return target abor t to initiator. set received ta rget abort bit in the target interface status register. set signaled ta rget abort bit in th e initiator interface status register. after pi7c8154a makes 2 24 (default) attempts of the same delayed read transaction on the target bus, pi7c8154a asserts p_serr# if the primary serr# enable bit is set (bit 8 of command register for secondary bus) and the delayed-write -non-delivery bit is not set. the delayed-write- non-delivery bit is bit 5 of p_serr# event disabl e register (offset 64h). pi7c8154a will report system error. see section 5.4 for a description of system error conditions. 2.11.4 target termination in itiated by pi7c8154a pi7c8154a can return a target retr y, target disconnect, or target abort to an initiator for reasons other than detection of that condition at the target interface. 2.11.4.1 target retry pi7c8154a returns a target retry to the initiator when it cannot accept write data or return read data as a result of internal conditions. pi7c8154a returns a target retry to an initiator when any of the following conditions is met: for delayed write transactions: ! the transaction is being entered in to the delayed transaction queue. ! transaction has already been entered into delaye d transaction queue, but target response has not yet been received. ! target response has been received but has not progressed to the head of the return queue. ! the delayed transaction queue is full, and the transaction cannot be queued. ! a transaction with the same address and command has been queued. ! a locked sequence is being propagated across pi 7c8154a, and the write transaction is not a locked transaction. ! the target bus is locked and the write transaction is a lo cked transaction. ! use more than 16 clocks to accept this transaction.
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 43 of 112 july 2004 revision 1.00 for delayed read transactions: ! the transaction is being entered in to the delayed transaction queue. ! the read request has already been queued , but read data is not yet available. ! data has been read from target, but it is not yet at head of the read data queue or a posted write transaction precedes it. ! the delayed transaction queue is full, and the transaction cannot be queued. ! a delayed read request with the same address and bus command has already been queued. ! a locked sequence is being propagated across pi 7c8154a, and the read transaction is not a locked transaction. ! pi7c78154b is currently discarding previously pre-fetched read data. ! the target bus is locked and the write transaction is a lo cked transaction. ! use more than 16 clocks to accept this transaction. for posted write transactions: ! the posted write data buffer does not have enough space for address and at least one dword of write data. ! a locked sequence is being propagated across pi 7c8154a, and the write transaction is not a locked transaction. ! when a target retry is returned to the initiator of a delayed transaction, the initiator must repeat the transaction with the same address and bus command as well as the data if it is a write transaction, within the time frame specified by the master timeout value. otherwise, the transaction is discarded from the buffers. 2.11.4.2 target disconnect pi7c8154a returns a target disconnect to an initia tor when one of the following conditions is met: ! pi7c8154a hits an internal address boundary. ! pi7c8154a cannot accept any more write data. ! pi7c8154a has no more read data to deliver. see section 2.6.4 for a description of write address boundaries, and section 2.7.3 for a description of read address boundaries. 2.11.4.3 target abort pi7c8154a returns a target abort to an initiator when one of the following conditions is met: ! pi7c8154a is returning a target abort from the intended target. ! when pi7c8154a returns a target abort to the initiator, it sets the signaled target abort bit in the status register correspondi ng to the initiator interface. 3 address decoding pi7c8154a uses three address ranges that control i/o and memory transaction forwarding. these address ranges are defined by base and limit addr ess registers in the configuration space. this chapter describes these address ranges, as we ll as isa-mode and vga-addressing support.
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 44 of 112 july 2004 revision 1.00 3.1 address ranges pi7c8154a uses the following addr ess ranges that determine which i/o and memory transactions are forwarded from the primary pci bus to the secondary pci bus, and from the secondary bus to the primary bus: ! two 32-bit i/o address ranges ! two 32-bit memory-mapped i/o (non-prefetchable memory) ranges ! two 32-bit prefetchable memory address ranges transactions falling within these ranges are forwarded downstream from the primary pci bus to the secondary pci bus. transactions falling outside these ranges are forwarded upstream from the secondary pci bus to the primary pci bus. no address translation is required in pi7c8154a. the addresses that are not marked for downstream are always forwarded upstream. 3.2 i/o address decoding pi7c8154a uses the following mech anisms that are defined in the configuration space to specify the i/o address space for downs tream and upstream forwarding: ! i/o base and limit address registers ! the isa enable bit ! the vga mode bit ! the vga snoop bit this section provides information on the i/o address registers and isa mode section 3.4 provides information on the vga modes. to enable downstream forwarding of i/o transactions, the i/o enable bit must be set in the command register in configuration space. all i/o tr ansactions initiated on the primary bus will be ignored if the i/o enable bit is not set. to en able upstream forwarding of i/o transactions, the master enable bit must be set in the command register. if the master-enable bit is not set, pi7c8154a ignores all i/o and memory transactions initiated on the secondary bus. the master-enable bit also allows upstream forw arding of memory transactions if it is set. caution if any configuration state affecting i/o transaction forwarding is changed by a configuration write operation on the primary bus at the same time that i/o transactions are ongoing on the secondary bus, pi7c8154a response to the secondary bus i/o transactions is not predictable. configure the i/o base and limit address registers, isa enable bit, vga mode bit, and vga snoop bit before setting i/o enable and master enable bits, and change them subsequently only when the primary and secondary pci buses are idle.
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 45 of 112 july 2004 revision 1.00 3.2.1 i/o base and limit address register pi7c8154a implements one set of i/o base and li mit address registers in configuration space that define an i/o address range per port downstream forwarding. pi7c8154a supports 32-bit i/o addressing, which allows i/o addresses downstream of pi7c8154a to be mapped anywhere in a 4gb i/o address space. i/o transactions with addresses that fall inside th e range defined by the i/o base and limit registers are forwarded downstream from the primary pci bus to the secondary pci bus. i/o transactions with addresses that fall outside this range are forwarded upstream from the secondary pci bus to the primary pci bus. the i/o range can be turned off by setting the i/o ba se address to a value greater than that of the i/o limit address. when the i/o range is turned off, all i/o trans-actions are forwarded upstream, and no i/o transactions are forwarded downstr eam. the i/o range has a minimum granularity of 4kb and is aligned on a 4kb boundary. the maximum i/o range is 4gb in size. the i/o base register consists of an 8-bit field at configuration address 1ch, and a 16-bit field at address 30h. the top 4 bits of the 8-bit field define bits [15:12] of the i/o base address. the bottom 4 bits read only as 1h to indicate that pi7c8154a supports 32-bit i/o addressing. bits [11:0] of the base address are assumed to be 0, which naturally ali gns the base address to a 4kb boundary. the 16 bits contained in the i/o base upper 16 bits register at configuration offset 30h define ad[31:16] of the i/o base address. all 16 bits are read/write. after primary bus reset or chip reset, the value of the i/o base address is initialized to 0000 0000h. the i/o limit register consists of an 8-bit field at configuration offset 1dh and a 16-bit field at offset 32h. the top 4 bits of the 8-bit field define bits [15:12] of the i/o limit address. the bottom 4 bits read only as 1h to indicate that 32-bit i/o addressing is supported. bits [11:0] of the limit address are assumed to be fffh, which naturally a ligns the limit address to the top of a 4kb i/o address block. the 16 bits contained in the i/o limit upper 16 bits register at configuration offset 32h define ad[31:16] of the i/o limit address. all 16 bits are read/write. after primary bus reset or chip reset, the value of the i/o lim it address is reset to 0000 0fffh. note: the initial states of the i/o base and i/o limit address registers define an i/o range of 0000 0000h to 0000 0fffh, which is the bottom 4kb of i/o space. write these registers with their appropriate values before setting either the i/o enable bit or the master enable bit in the command register in configuration space. 3.2.2 isa mode pi7c8154a supports isa mode by providing an isa enable bit in the bridge control register in configuration space. isa mode modifies the respon se of pi7c8154a inside the i/o address range in order to support mapping of i/o space in the pr esence of an isa bus in the system. this bit only affects the response of pi7c8154a when the transaction falls inside the address range defined by the i/o base and limit address registers, and only wh en this address also falls inside the first 64kb of i/o space (address bits [31:16] are 0000h). when the isa enable bit is set, pi7c8154a doe s not forward downstream any i/o transactions addressing the top 768 bytes of each aligned 1kb block. only those transactions addressing the bottom 256 bytes of an aligned 1kb block inside the base and limit i/o address range are forwarded downstream. transactions above the 64kb i/o address boundary are forwarded as defined by the address range defined by the i/o base and limit registers.
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 46 of 112 july 2004 revision 1.00 accordingly, if the isa enable bit is set, pi7c 8154a forwards upstream those i/o transactions addressing the top 768 bytes of each aligned 1kb block within the first 64kb of i/o space. the master enable bit in the command configuration re gister must also be set to enable upstream forwarding. all other i/o transactions initiated on the secondary bus are forwarded upstream only if they fall outside the i/o address range. when the isa enable bit is set, devices down stream of pi7c8154a can have i/o space mapped into the first 256 bytes of each 1kb chunk below the 64kb boundary, or anywhere in i/o space above the 64kb boundary. 3.3 memory address decoding pi7c8154a has three mechanisms for defining memory address ranges for forwarding of memory transactions: ! memory-mapped i/o base and limit address registers ! prefetchable memory base and limit address registers ! vga mode this section describes the first two mechanisms . section 3.4.1 describes vga mode. to enable downstream forwarding of memory transactions , the memory enable bit must be set in the command register in configuration space. to enable upstream forwarding of memory transactions, the master-enable bit must be set in the comma nd register. the master-enable bit also allows upstream forwarding of i/o transactions if it is set. caution if any configuration state affecting memory transaction forwarding is changed by a configuration write operation on the primary bus at the same time that memory transactions are ongoing on the secondary bus, response to the secondary bus memory transactions is not predictable. configure the memory-mapped i/o base and limit address re gisters, prefetchable memory base and limit address registers, and vga mode bit before setting the memory enable and master enable bits, and change them subsequently only when the primary and secondary pci buses are idle. 3.3.1 memory-mapped i/o base and limit address registers memory-mapped i/o is also referred to as no n-prefetchable memory. memory addresses that cannot automatically be pre-fetched but that ca n be conditionally pre-fetched based on command type should be mapped into this space. read tr ansactions to non-prefet chable space may exhibit side effects; this space may have non-memory-lik e behavior. pi7c8154a prefetches in this space only if the memory read line or memory read mu ltiple commands are used; transactions using the memory read command are limited to a single data transfer. the memory-mapped i/o base address and memory-mapped i/o limit address registers define an address range that pi7c8154a uses to determine when to forward memory commands. pi7c8154a forwards a memory transaction fr om the primary to the secondar y interface if the transaction address falls within the memory-mapped i/o address range. pi7c8154a ignores memory transactions initiated on the secondary interface th at fall into this address range. any transactions that fall outside this address range are ignored on the primary interface and are forwarded upstream from the secondary interface (provided that they do not fall into the prefetchable memory range or are not forwarded downstrea m by the vga mechanism).
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 47 of 112 july 2004 revision 1.00 the memory-mapped i/o range supports 32-bit addressing only. the pci-to-pci bridge architecture specification does not provide for 64-bit addressing in the memory-mapped i/o space. the memory-mapped i/o address range has a granularity and alignment of 1mb. the maximum memory-mapped i/o address range is 4gb. the memory-mapped i/o address range is defined by a 16-bit memory-mapped i/o base address register at configuration offset 20h and by a 16-bit memory-mapped i/o limit address register at offset 22h. the top 12 bits of each of these registers correspond to bits [31:20] of the memory address. the low 4 bits are hardwired to 0. the lowest 20 bits of the memory-mapped i/o base address are assumed to be 0 0000h, which results in a natural alignment to a 1mb boundary. the lowest 20 bits of the memory-mapped i/o limit address are assumed to be fffffh, which results in an alignment to the top of a 1mb block. note: the initial state of the memory-mapped i/o base address register is 0000 0000h. the initial state of the memory-mapped i/o limit address register is 000f ffffh. note that the initial states of these registers define a memory-mapped i/o range at the bottom 1mb block of memory. write these registers with their appropriate values before setting either the memory enable bit or the master enable bit in the command register in configuration space. to turn off the memory-mapped i/o address range, write the memory-mapped i/o base address register with a value greater than that of the memory-mappe d i/o limit address register. 3.3.2 prefetchable memory base and limit address registers locations accessed in the prefetchable memory address range must have true memory-like behavior and must not exhibit side effects when re ad. this means that extra reads to a prefetchable memory location must have no side effects. pi7c8154a pre-fetches for all types of memory read commands in this address space. the prefetchable memory base address and prefetch able memory limit address registers define an address range that pi7c8154a uses to determine when to forward memory commands. pi7c8154a forwards a memory transaction fr om the primary to the secondar y interface if the transaction address falls within the pref etchable memory address rang e. pi7c8154a ignores memory transactions initiated on the secondary interface that fall into this address range. pi7c8154a does not respond to any transactions that fall outside this address range on th e primary interface and forwards those transactions upstream from the seco ndary interface (provided that they do not fall into the memory-mapped i/o range or are not forwarded by the vga mechanism). the prefetchable memory range supports 64-bit addressing and provides additional registers to define the upper 32 bits of the memory address range, the prefetchable memory base address upper 32 bits register, and the prefetchable memory limit address upper 32 bits register. for address comparison, a single address cycle (32-bit address) prefetchable memory transaction is treated like a 64-bit address transaction where the upper 32 bits of the address are equal to 0. this upper 32-bit value of 0 is compared to the prefetchable memo ry base address upper 32 bits register and the prefetchable memory limit address upper 32 bits register. the prefetchable memory base address upper 32 bits register must be 0 to pass any single address cycle transactions downstream. prefetchable memory address range has a granul arity and alignment of 1mb. maximum memory address range is 4gb when 32-bit addressing is be ing used. prefetchable memory address range is defined by a 16-bit prefetchable memory base address register at configuration offset 24h and by a 16-bit prefetchable memory limit a ddress register at offset 26h. th e top 12 bits of each of these
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 48 of 112 july 2004 revision 1.00 registers correspond to bits [31:20] of the memory address. the lowest 4 bits are hardwired to 1h. the lowest 20 bits of the pref etchable memory base address ar e assumed to be 0 0000h, which results in a natural alignment to a 1mb boundary. the lowest 20 bits of the prefetchable memory limit address are assumed to be fffffh, which results in an alignment to the top of a 1mb block. note: the initial state of the prefetchable memory base address register is 0000 0000h. the initial state of the prefetchable memory limit address register is 000f ffffh. note that the initial states of these registers define a prefetchable memory range at the bottom 1mb block of memory. write these registers with their appropriate values before setting either the memory enable bit or the master enable bit in the command register in configuration space. to turn off the prefetchable memory address rang e, write the prefetchable memory base address register with a value greater than that of the prefetchable memory limit address register. the entire base value must be greater than the entire limit value, meaning that the upper 32 bits must be considered. therefore, to disable the address range, the upper 32 bits registers can both be set to the same value, while the lower base register is set gr eater than the lower limit register. otherwise, the upper 32-bit base must be greater than the upper 32-bit limit. 3.3.3 prefetchable memory 64-bit addressing registers pi7c8154a supports 64-bit memory address decoding for forwarding of dual address memory transactions. dual address cycle is used for 64-bit addressing. th e first address phase of the dual address cycle contains the low 32 bits of the address and the s econd address phase contains the high 32 bits. the high 32 bits must never be 0 during a dual address cycle. the prefetchable memory address range is define d by implementing the prefetchable memory base address upper 32 bits register an d the prefetchable memory limit address upper 32 bits register. the prefetchable address spac e can be defined as either: ! residing entirely in the first 4gb of memory ! residing entirely above the first 4gb of memory ! crossing the first 4gb memory boundary if the prefetchable memory space on the secondary bus resides entirely in the first 4gb of memory, both upper 32 bit register must be set to 0. pi7c8154a then ignores all dual address cycles initiated on the primary interface and forwards all dual addr ess transactions initiated on the secondary interface upstream. if the prefetchable memory space on the secondary bus resides entirely above the first 4gb of memory, both the prefetchable memory base addr ess upper 32 bit register and the prefetchable memory limit address upper 32 bit register must be initialized to nonzero values. pi7c8154a ignores all single address memory transactions in itiated on the primary an d forwards all single address memory transactions initiated on the secondary upstream, unless the memory falls within the memory mapped i/o or vga memory range. a dual address memory transaction is forwarded downstream from the primary if it falls within the address range defined by the prefetchable memory base address, prefetchable memory base address upper 32 bits, prefetchable memory limit address, and prefetchable memory limit address uppe r 32 bits. if the dual address cycle initiated on the secondary falls outside this address range, it is forwarded upstream to the primary. pi7c8154a does not respond to a dual address cycle initiated on the primary that falls outside this address range, or to a dual address cycle initiated on th e secondary that falls within the address range.
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 49 of 112 july 2004 revision 1.00 if the prefetchable memory space on the secondary bus resides on top of the 4gb boundary, the prefetchable memory base address upper 32 bit re gister is set to 0 and the prefetchable memory limit address upper 32 bit register is initialized to a nonzero value. single address cycle memory transactions are compared to the prefetchable memory base addres s register only. a transaction initiated on the primary is forwarde d downstream if the address is greater than or equal to the base address. a transaction initiated on the secondary is forwarded upstream if the address is less than the base address. dual address cycles are compar ed to the prefetchable memory limit address and the prefetchable memory limit addr ess upper 32 bit register. if the address of the dual address cycle is less than or equal to the limit, the tran saction is forwarded downstream from the primary and is ignored on the secondary. if the address of the dual address cycle is greater than this limit, the transaction is ignored on the primary and is forwarded upstream from the secondary. the prefetchable memory base address upper 32 bit register is located at offset 28h of the configuration register and the pref etchable memory limit address upper 32 bit register is located at offset 2ch. both registers are reset to 0. 3.4 vga support pi7c8154a provides two modes for vga support: ! vga mode, supporting vga-compatible addressing ! vga snoop mode, supporting vga palette forwarding 3.4.1 vga mode when a vga-compatible device exists downstream from pi7c8154a, set the vga mode bit in the bridge control register in configuration space to enable vga mode. when pi7c8154a is operating in vga mode, it forwards downstream those transactions addressing the vga frame buffer memory and vga i/o registers, regardless of the values of the base and limit address registers. pi7c8154a ignores transactions initiated on the secondary interface addressing these locations. the vga frame buffer co nsists of the following memory address range: 000a 0000h?000b ffffh read transactions to frame buffer memory are tr eated as non-prefetchab le. pi7c8154a requests only a single data transfer from the target, and read byte enable bits are forwarded to the target bus. the vga i/o addresses are in the range of 3b0h?3bbh and 3c0h?3dfh i/o. these i/o addresses are aliases every 1kb throughout the first 64kb of i/o space. this means that address bits [5:10] are not decoded and can be any value, while address bits [31:16] must be all 0?s. vga bios addresses starting at c0000h are not decoded in vga mode. 3.4.2 vga snoop mode pi7c8154a provides vga snoop mode, allowing for vga palette write transactions to be forwarded downstream. this mode is used when a graphics device downstream from pi7c8154a needs to snoop or respond to vga palette write transactions. to enable the mode, set the vga
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 50 of 112 july 2004 revision 1.00 snoop bit in the command regist er in configuration space. note that pi7c8154a claims vga palette write transactions by asserting devsel# in vga snoop mode. when vga snoop bit is set, pi7c8154a forwards downstream transactions within the 3c6h, 3c8h and 3c9h i/o addresses space. note that these ad dresses are also forwarded as part of the vga compatibility mode previously described. again, address bits [15:10] are not decoded, while address bits [31:16] must be equal to 0, which means that these addresses are aliases every 1kb throughout the first 64kb of i/o space. note: if both the vga mode bit and the vga snoop bit are set, pi7c8154a behaves in the same way as if only the vga mode bit were set. 4 transaction ordering to maintain data coherency and consistency, pi7c8154a complies with the ordering rules set forth in the pci local bus specification, revision 2.2, for transactions crossing the bridge. this chapter describes the ordering rules that control transaction forwarding across pi7c8154a. 4.1 transactions governed by ordering rules ordering relationships are established for the following classes of transactions crossing pi7c8154a: posted write transactions, comprised of memory write and memory write and invalidate transactions. posted write transactions complete at the source before they complete at the destination; that is, data is written into intermediate data buffers before it reaches the target. delayed write request transactions, comprised of i/o write and configuration write transactions. delayed write requests are terminated by target retry on the initiator bus and are queued in the delayed transaction queue. a delayed write transaction must complete on the target bus before it completes on the initiator bus. delayed write completion transactions, comprised of i/o write and configuration write transactions. delayed write completion transactions complete on th e target bus, and the target response is queued in the buffers. a delayed write completion transactio n proceeds in the direction opposite that of the original delayed write request; that is, a delaye d write completion transaction proceeds from the target bus to the initiator bus. delayed read request transactions, comp rised of all memory read, i/o read, and configuration read transactions. delayed read requests are terminated by target retry on the initiator bus and are queued in the delayed transaction queue. delayed read completion transactions, comprised of all memory read, i/o read, & configuration read transactions. delayed read completion transactions complete on th e target bus, and the read data is queued in the read data buffers. a delayed read completion trans action proceeds in the dir ection opposite that of
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 51 of 112 july 2004 revision 1.00 the original delayed read request; that is, a dela yed read completion transaction proceeds from the target bus to the initiator bus. pi7c8154a does not combine or merge write transactions: ! pi7c8154a does not combine separate write trans actions into a single write transaction?this optimization is best implemented in the originating master. ! pi7c8154a does not merge bytes on separate masked write transactions to the same dword address?this optimization is also best implemented in the originating master. ! pi7c8154a does not collapse sequ ential write transactions to the same address into a single write transaction - the pci local bus specification does not permit this combining of transactions. 4.2 general ordering guidelines independent transactions on primary and secondary buses have a relationship only when those transactions cross pi7c8154a. the following general ordering guidelines govern transactions crossing pi7c8154a: ! the ordering relationship of a transaction with respect to other transactions is determined when the transaction completes, that is, when a trans action ends with a termination other than target retry. ! requests terminated with target retry can be accepted and completed in any order with respect to other transactions that have been terminated with target retry. if the order of completion of delayed requests is important, the initiator shoul d not start a second de layed transaction until the first one has been completed. if more than one delayed transaction is initiated, the initiator should repeat all delayed transaction requests , using some fairness algorithm. repeating a delayed transaction cannot be contingent on completion of another delayed transaction. otherwise, a deadlock can occur. ! write transactions flowing in one direction have no ordering requirements with respect to write transactions flowing in the other direction. pi 7c8154a can accept posted write transactions on both interfaces at the same time, as well as initia te posted write transactions on both interfaces at the same time. ! the acceptance of a posted memory write transaction as a target can never be contingent on the completion of a non-locked, non-posted transac tion as a master. this is true for pi7c8154a and must also be true for other bus agents. otherwise, a deadlock can occur. ! pi7c8154a accepts posted write transactions, re gardless of the state of completion of any delayed transactions being forwarded across pi7c8154a. 4.3 ordering rules table 4-1 shows the ordering relationships of all the transactions and refers by number to the ordering rules that follow. table 4-1 summary of transaction ordering pass posted write delayed read request delayed write request delayed read completion delayed write completion posted write no 1 yes 5 yes 5 yes 5 yes 5 delayed read request no 2 no no yes yes
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 52 of 112 july 2004 revision 1.00 pass posted write delayed read request delayed write request delayed read completion delayed write completion delayed write request no 4 no no yes yes delayed read completion no 3 yes yes no no delayed write completion yes yes yes no no note: the superscript accompanying some of the table en tries refers to any applicable ordering rule listed in this section. many entries are not gov erned by these ordering rules; therefore, the implementation can choose whether or not the transactions pass each other. the entries without superscripts reflect the pi7c8154a?s implementation choices. the following ordering rules describe the transac tion relationships. each ordering rule is followed by an explanation, and the ordering rules are referred to by number in table 4-1. these ordering rules apply to posted write transactions, delayed write and read requests, and delayed write and read completion transactions crossing pi7c8154a in the same direction. note that delayed completion transactions cross pi7c8154a in the direction opposite that of the corresponding delayed requests. 1. posted write transactions must complete on the target bus in the order in which they were received on the initiator bus. the subsequent post ed write transaction can be setting a flag that covers the data in the first posted write transac tion; if the second transaction were to complete before the first transaction, a device checking th e flag could subsequently consume stale data. 2. a delayed read request traveling in the same direction as a previous ly queued posted write transaction must push the posted write data ahead of it. the posted write transaction must complete on the target bus before the delayed read reques t can be attempted on the target bus. the read transaction can be to the same location as the write data, so if the read transaction were to pass the write transaction, it would return stale data. 3. a delayed read completion must ??pull?? ahead of previously queued posted write data traveling in the same direction. in this case, the read data is traveling in the same direction as the write data, and the initiator of the read transaction is on the same side of pi7c8154a as the target of the write transaction. the posted write tran saction must complete to the target before the read data is returned to the initiator. the read transaction can be a read ing to a status register of the initiator of the posted write data and therefore should not comp lete until the write transaction is complete. 4. delayed write requests cannot pass previously queued posted write data. for posted memory write transactions, the delayed write transaction can set a flag that covers the data in the posted write transaction. if the delayed write request we re to complete before the earlier posted write transaction, a device checking the flag could subsequently consume stale data. 5. posted write transactions must be given opportunities to pass delayed read and write requests and completions. otherwise, deadlocks may occur when some bridges which support delayed transactions and other bridges which do not support delayed transactions are being used in the same system. a fairness algorithm is used to arbitrat e between the posted write queue and the delayed transaction queue. 4.4 data synchronization data synchronization refers to the relationship between interrupt signaling and data delivery. the pci local bus specification , revision 2.2, provides the following alternative methods for synchronizing data and interrupts:
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 53 of 112 july 2004 revision 1.00 ! the device signaling the interrupt performs a read of the data just written (software). ! the device driver performs a read operation to any register in the interrupting device before accessing data written by the device (software). ! system hardware guarantees that write buffers are flushed before interrupts are forwarded. pi7c8154a does not have a hardware mechanism to guarantee data synchronization for posted write transactions. therefore, all posted write tr ansactions must be followed by a read operation, either from the device to the location just written (or some other location along the same path), or from the device driver to one of the device registers. 5 error handling pi7c8154a checks, forwards, and generates parity on both the primary and secondary interfaces. to maintain transparency, pi7c8154a always trie s to forward the existing parity condition on one bus to the other bus, along with address and data . pi7c8154a always attempts to be transparent when reporting errors, but this is not always possible, given the presence of posted data and delayed transactions. to support error reporting on the pci bus, pi7c8154a implements the following: ! perr# and serr# signals on both th e primary and secondary interfaces ! primary status and secondary status registers ! the device-specific p_serr# event disable register this chapter provides detailed information about how pi7c8154a handles errors. it also describes error status reporting and error operation disabling. 5.1 address parity errors pi7c8154a checks address parity fo r all transactions on both buses, for all address and all bus commands. when pi7c8154a detect s an address parity error on the primary interface, the following events occur: ! if the parity error response bit is set in the command register, pi7c8154a does not claim the transaction with p_devsel#; this may allow the tr ansaction to terminate in a master abort. if parity error response bit is not set, pi7c8154a proceeds normally a nd accepts the transaction if it is directed to or across pi7c8154a. ! pi7c8154a sets the detected parity error bit in the status register. ! pi7c8154a asserts p_serr# and sets signaled syst em error bit in the status register, if both the following conditions are met: ! the serr# enable bit is set in the command register ! the parity error response bit is set in the command register when pi7c8154a detects an addres s parity error on the secondary interface, the following events occur: ! if the parity error response bit is set in the br idge control register, pi 7c8154a does not claim the transaction with s_devsel#; this may allo w the transaction to terminate in a master
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 54 of 112 july 2004 revision 1.00 abort. if parity error resp onse bit is not set, pi7c8154 a proceeds normally and accepts transaction if it is directed to or across pi7c8154a. ! pi7c8154a sets the detected parity erro r bit in the secondary status register ! pi7c8154a asserts p_serr# and sets signaled system error bit in status register, if both of the following conditions are met: ! the serr# enable bit is set in the command register ! the parity error response bit is set in the bridge control register 5.2 data parity errors when forwarding transactions, pi7c8154a attempts to pass the data parity condition from one interface to the other unchanged, whenever possibl e, to allow the master and target devices to handle the error condition. the following sections describe, for each type of transaction, the sequence of events that occurs when a parity error is detected and the way in which the parity condition is forwarded across pi7c8154a. 5.2.1 configuration write transact ions to configuration space when pi7c8154a detects a data parity error duri ng a type 0 configuration write transaction to pi7c8154a configuration space, the following events occur: if the parity error response bit is set in the command register, pi7c8154a asserts p_trdy# and writes the data to the configuration register. pi 7c8154a also asserts p_perr#. if the parity error response bit is not set, pi7c8154a does not assert p_perr#. pi7c8154a sets the detected parity error bit in th e status register, regardless of the state of the parity error response bit. 5.2.2 read transactions when pi7c8154a detects a parity error during a read transaction, the target drives data and data parity, and the initiator checks parity and conditionally asserts perr#. for downstream transactions, when pi7c8154a detects a read data parity error on the secondary bus, the following events occur: ! pi7c8154a asserts s_perr# two cy cles following the data transf er, if the secondary interface parity error response bit is set in the bridge control register. ! pi7c8154a sets the detected parity erro r bit in the secondary status register. ! pi7c8154a sets the data parity detected bit in the secondary status register, if the secondary interface parity error response bit is set in the bridge control register. ! pi7c8154a forwards the bad par ity with the data back to the initiator on the primary bus. if the data with the bad parity is pre-fetched an d is not read by the initiator on the primary bus, the data is discarded and the data with ba d parity is not returned to the initiator. ! pi7c8154a completes the transaction normally.
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 55 of 112 july 2004 revision 1.00 for upstream transactions, when pi7c8154a detects a read data parity error on the primary bus, the following events occur: ! pi7c8154a asserts p_perr# 2 cycles following the data transfer, if the primary interface parity error response bit is set in the command register. ! pi7c8154a sets the detected parity erro r bit in the primary status register. ! pi7c8154a sets the data parity detected bit in the primary status re gister, if the primary interface parity-error-r esponse bit is set in the command register. ! pi7c8154a forwards the bad parity with the data back to the initiator on the secondary bus. if the data with the bad parity is pre-fetched and is not read by the initiator on the secondary bus, the data is discarded and the data with ba d parity is not returned to the initiator. ! pi7c8154a completes the transaction normally. pi7c8154a returns to the initiator the data and parity that wa s received from the target. when the initiator detects a parity error on this read data and is enabled to report it, the initiator asserts perr# two cycles after the data transfer occurs. it is assumed that the initiator takes responsibility for handling a parity error condition; therefore, when pi7c8154a detects perr# asserted while returning read data to the initiator, pi7c8154a does not take any further action and completes the transaction normally. 5.2.3 delayed write transactions when pi7c8154a detects a data parity error during a delayed write transaction, the initiator drives data and data parity, and the target checks parity and conditionally asserts perr#. for delayed write transactions, a parity error can occur at the following times: ! during the original delayed write request transaction ! when the initiator repeats the delayed write request transaction ! when pi7c8154a completes the delayed write transaction to the target when a delayed write transaction is normally queued, the address, command, address parity, data, byte enable bits, and data parity are all captured an d a target retry is returned to the initiator. when pi7c8154a detects a parity error on the write data for the initial delayed write request transaction, the following events occur: ! if the parity-error-response bit corresponding to the initiator bus is set, pi7c8154a asserts trdy# to the initiator and the transaction is not queued. if multiple data phases are requested, stop# is also asserted to cause a target di sconnect. two cycles after the data transfer, pi7c8154a also asserts perr#. ! if the parity-error-response bit is not set, pi7c 8154a returns a target re try. it queues the transaction as usual. pi7c8154a does not assert perr#. in this case, the initiator repeats the transaction. ! pi7c8154a sets the detected-parity-error bit in th e status register corresponding to the initiator bus, regardless of the state of the parity-error-response bit. note: if parity checking is turned off and data parity errors have occurred for queued or subsequent delayed write transactions on the initiator bus, it is possible that the initiator?s re-attempts of the write transaction may not match the original queu ed delayed write information contained in the delayed transaction queue. in this case, a master timeout condition may occur, possibly resulting in a system error (p_serr# assertion).
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 56 of 112 july 2004 revision 1.00 for downstream transactions, when pi7c8154a is de livering data to the target on the secondary bus and s_perr# is asserted by the target, the following events occur: ! pi7c8154a sets the secondary interface data pa rity detected bit in the secondary status register, if the secondary parity error respons e bit is set in the bridge control register. ! pi7c8154a captures the parity er ror condition to forward it back to the initiator on the primary bus. similarly, for upstream transactions, when pi7c 8154a is delivering data to the target on the primary bus and p_perr# is asserted by the target, the following events occur: ! pi7c8154a sets the primary interface data-parity -detected bit in the st atus register, if the primary parity-error-response bit is set in the command register. ! pi7c8154a captures the parity error condition to forward it back to the initiator on the secondary bus. a delayed write transaction is completed on the initiator bus when the initiator repeats the write transaction with the same address, command, da ta, and byte enable bits as the delayed write command that is at the head of the posted data queue. note that the parity bit is not compared when determining whether the transaction matches those in the delayed transaction queues. two cases must be considered: ! when parity error is detected on the initiator bus on a subsequent re-attempt of the transaction and was not detected on the target bus. ! when parity error is forwarded back from the target bus for downstream delayed write transactions, when th e parity error is detected on the initiator bus and pi7c8154a has write status to return, the following events occur: ! pi7c8154a first asserts p_trdy# and then assert s p_perr# two cycles later, if the primary interface parity-error-r esponse bit is set in the command register. ! pi7c8154a sets the primary interface parity-e rror-detected bit in the status register. ! because there was not an exact data and parity ma tch, the write status is not returned and the transaction remains in the queue. similarly, for upstream delayed write transactions, when the parity error is detected on the initiator bus and pi7c8154a has write status to return, the following events occur: ! pi7c8154a first asserts s_trdy# and then asserts s_perr# two cycles later; if the secondary interface parity-error-response bit is set in the bridge control register (offset 3ch). ! pi7c8154a sets the secondary interface parity -error-detected bit in the secondary status register. ! because there was not an exact data and parity ma tch, the write status is not returned and the transaction remains in the queue. for downstream transactions, where the parity erro r is being passed back from the target bus and the parity error condition was not originally detected on the initiator bus, the following events occur: ! bridge asserts p_perr# two cycles after the da ta transfer, if the following are both true: ! the parity-error-response bit is set in the command register of the primary interface ! the parity-error-response bit is set in the brid ge control register of the secondary interface
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 57 of 112 july 2004 revision 1.00 ! bridge completes the transaction normally. for upstream transactions, when th e parity error is being passed back from the target bus and the parity error condition was not originally detected on the initiator bus, the following events occur: ! bridge asserts s_perr# two cycles after the da ta transfer, if the following are both true: ! the parity error response bit is set in th e command register of the primary interface. ! the parity error response bit is set in the brid ge control register of the secondary interface. ! bridge completes the transaction normally. 5.2.4 posted write transactions during downstream posted write transactions, when th e bridge responds as a target, it detects a data parity error on the initiator (primary) bus and the following events occur: ! bridge asserts p_perr# two cycles after the data transfer, if the parity error response bit is set in the command register of primary interface. ! bridge sets the parity error detected bit in the status register of the primary interface. ! bridge captures and forwards the bad parity condition to the secondary bus. ! bridge completes the transaction normally. similarly, during upstream posted write transac tions, when the bridge responds as a target, it detects a data parity error on the initiator (secondary) bus, the following events occur: ! bridge asserts s_perr# two cycles after the data transfer, if the parity error response bit is set in the bridge control register of the secondary interface. ! bridge sets the parity error detected bit in the status register of the secondary interface. ! bridge captures and forwards the bad parity condition to the primary bus. ! bridge completes the transaction normally. during downstream write trans actions, when a data parity error is reported on the target (secondary) bus by the target?s assertion of s_perr#, the following events occur: ! bridge sets the data parity detected bit in the st atus register of secondary interface, if the parity error response bit is set in the bridge co ntrol register of the secondary interface. ! bridge asserts p_serr# and sets the signaled system error bit in the status register, if all the following conditions are met: ! the serr# enable bit is set in the command register. ! the posted write parity error bit of p_se rr# event disable register is not set. ! the parity error response bit is set in the brid ge control register of the secondary interface. ! the parity error response bit is set in th e command register of the primary interface. ! bridge has not detected the parity error on the primary (initiator) bus which the parity error is not forwarded from the pr imary bus to the secondary bus. during upstream write transactions, when a data par ity error is reported on the target (primary) bus by the target?s assertion of p_perr#, the following events occur:
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 58 of 112 july 2004 revision 1.00 ! bridge sets the data parity detected bit in the st atus register, if the parity error response bit is set in the command register of the primary interface. ! bridge asserts p_serr# and sets the signaled system error bit in the status register, if all the following conditions are met: ! the serr# enable bit is set in the command register ! the parity error response bit is set in the brid ge control register of the secondary interface ! the parity error response bit is set in the command register of the primary interface ! bridge has not detected the parity error on the secondary (initiator) bus, which the parity error is not forwarded from the secondary bus to the primary bus assertion of p_serr# is used to signal the par ity error condition when the initiator does not know that the error occurred. b ecause the data has already been delivered with no er rors, there is no other way to signal this information back to the initia tor. if the parity error has forwarded from the initiating bus to the target bus, p_serr# will not be asserted. 5.3 data parity error reporting in the previous sections, the responses of the bridge to data parity errors are presented according to the type of transaction in progress. this section or ganizes the responses of the bridge to data parity errors according to the status b its that the bridge sets and the signals that it asserts. table 5-1 shows setting the detected parity error bit in the status register, corresponding to the primary interface. this bit is se t when pi7c8154a detects a parity error on the pr imary interface. table 5-1 setting the primary in terface detected parity error bit (bit 31 of offset 04h) primary detected parity error bit transaction type direction bus where error was detected primary/ secondary parity error response bits 0 read downstream primary x / x 0 read downstream secondary x / x 1 read upstream primary x / x 0 read upstream secondary x / x 1 posted write downstream primary x / x 0 posted write downstream secondary x / x 0 posted write upstream primary x / x 0 posted write upstream secondary x / x 1 delayed write downstream primary x / x 0 delayed write downstream secondary x / x 0 delayed write upstream primary x / x 0 delayed write upstream secondary x / x note: x=don?t care table 5-2 shows setting the detected parity error b it in the secondary status register, corresponding to the secondary interface. this bit is set when pi7c8154a detects a parity error on the secondary interface. table 5-2 setting the secondary interface detected parity error bit secondary detected parity error bit transaction type direction bus where error was detected primary/ secondary parity error response bits 0 read downstream primary x / x 1 read downstream secondary x / x
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 59 of 112 july 2004 revision 1.00 secondary detected parity error bit transaction type direction bus where error was detected primary/ secondary parity error response bits 0 read upstream primary x / x 0 read upstream secondary x / x 0 posted write downstream primary x / x 0 posted write downstream secondary x / x 0 posted write upstream primary x / x 1 posted write upstream secondary x / x 0 delayed write downstream primary x / x 0 delayed write downstream secondary x / x 0 delayed write upstream primary x / x 1 delayed write upstream secondary x / x note: x=don?t care table 5-3 shows setting data parity detected bit in th e primary interface?s status register. this bit is set under the following conditions: ! pi7c8154a must be a master on the primary bus. ! the parity error response bit in the command register, correspon ding to the primary interface, must be set. ! the p_perr# signal is detected asserted or a parity error is detected on the primary bus. table 5-3 setting the pr imary interface data pari ty detected bit (bit 24 of offset 04h) primary data parity bit transaction type direction bus where error was detected primary / secondary parity error response bits 0 read downstream primary x / x 0 read downstream secondary x / x 1 read upstream primary 1 / x 0 read upstream secondary x / x 0 posted write downstream primary x / x 0 posted write downstream secondary x / x 1 posted write upstream primary 1 / x 0 posted write upstream secondary x / x 0 delayed write downstream primary x / x 0 delayed write downstream secondary x / x 1 delayed write upstream primary 1 / x 0 delayed write upstream secondary x / x note: x=don?t care table 5-4 shows setting the data parity detected b it in the status register of secondary interface. this bit is set under the following conditions: ! the pi7c8154a must be a master on the secondary bus. ! the parity error response bit must be set in th e bridge control register of secondary interface. ! the s_perr# signal is detected asserted or a pa rity error is detected on the secondary bus. table 5-4 setting the secondary interface data parity detected bit secondary detected parity detected bit transaction type direction bus where error was detected primary / secondary parity error response bits 0 read downstream primary x / x 1 read downstream secondary x / 1 0 read upstream primary x / x 0 read upstream secondary x / x 0 posted write downstream primary x / x 1 posted write downstream secondary x / 1
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 60 of 112 july 2004 revision 1.00 secondary detected parity detected bit transaction type direction bus where error was detected primary / secondary parity error response bits 0 posted write upstream primary x / x 0 posted write upstream secondary x / x 0 delayed write downstream primary x / x 1 delayed write downstream secondary x / 1 0 delayed write upstream primary x / x 0 delayed write upstream secondary x / x note: x=don?t care table 5-5 shows assertion of p_perr#. this signal is set under the following conditions: ! pi7c8154a is either the target of a write transaction or the initiato r of a read transaction on the primary bus. ! the parity-error-response bit must be set in the command register of primary interface. ! pi7c8154a detects a data parity error on the primary bus or detects s_perr# asserted during the completion phase of a downstr eam delayed write transaction on the target (secondary) bus. table 5-5 assertion of p_perr# p_perr# transaction type direction bus where error was detected primary/ secondary parity error response bits 1 (de-asserted) read downstream primary x / x 1 read downstream secondary x / x 0 (asserted) read upstream primary 1 / x 1 read upstream secondary x / x 0 posted write downstream primary 1 / x 1 posted write downstream secondary x / x 1 posted write upstream primary x / x 1 posted write upstream secondary x / x 0 delayed write downstream primary 1 / x 0 2 delayed write downstream secondary 1 / 1 1 delayed write upstream primary x / x 1 delayed write upstream secondary x / x notes: x=don?t care 2 =the parity error was detected on the target (secondary) bus but not on the initiator (primary) bus. table 5-6 shows assertion of s_perr# that is set under the following conditions: ! pi7c8154a is either the target of a write transaction or the initiato r of a read transaction on the secondary bus. ! the parity error response bit must be set in th e bridge control register of secondary interface. ! pi7c8154a detects a data parity error on th e secondary bus or detects p_perr# asserted during the completion phase of an upstream dela yed write transaction on the target (primary) bus. table 5-6 assertion of s_perr# s_perr# transaction type direction bus where error was detected primary/ secondary parity error response bits 1 (de-asserted) read downstream primary x / x 0 (asserted) read downstream secondary x / 1 1 read upstream primary x / x 1 read upstream secondary x / x 1 posted write downstream primary x / x 1 posted write downstream secondary x / x 1 posted write upstream primary x / x 0 posted write upstream secondary x / 1 1 delayed write downstream primary x / x
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 61 of 112 july 2004 revision 1.00 s_perr# transaction type direction bus where error was detected primary/ secondary parity error response bits 1 delayed write downstream secondary x / x 0 2 delayed write upstream primary 1 / 1 0 delayed write upstream secondary x / 1 note: x=don?t care 2 =the parity error was detected on the target (seco ndary) bus but not on the initiator (primary) bus. table 5-7 shows assertion of p_serr#. this signal is set under the following conditions: ! pi7c8154a has detected p_perr# asserted on an upstream posted write transaction or s_perr# asserted on a downstr eam posted write transaction. ! pi7c8154a did not detect the parity error as a target of the posted write transaction. ! the parity error response bit on the command register and the parity error response bit on the bridge control register must both be set. ! the serr# enable bit must be set in the command register. table 5-7 assertion of p_serr# for data parity errors p_serr# transaction type direction bus where error was detected primary / secondary parity error response bits 1 (de-asserted) read downstream primary x / x 1 read downstream secondary x / x 1 read upstream primary x / x 1 read upstream secondary x / x 1 posted write downstream primary x / x 0 2 (asserted) posted write downstream secondary 1 / 1 0 3 posted write upstream primary 1 / 1 1 posted write upstream secondary x / x 1 delayed write downstream primary x / x 1 delayed write downstream secondary x / x 1 delayed write upstream primary x / x 1 delayed write upstream secondary x / x note: x=don?t care 5.4 system error (serr#) reporting pi7c8154a uses the p_serr# signal to report conditionally a number of system error conditions in addition to the special case parity error conditions described in section 5.2.3. whenever assertion of p_serr# is discussed in this document, it is assumed that the following conditions apply: ! for the bridge to assert p_serr# for any reason, the serr# enable bit must be set in the command register. ! whenever the bridge asserts p_serr#, pi7c8154a must also set the sign aled system error bit in the status register. in compliance with the pci-to-pci bridge archit ecture specification, the bridge asserts p_serr# when it detects the secondary serr# input, s_serr#, asserted and the serr# forward enable bit is set in the bridge control register. in addition, th e bridge also sets the rece ived system error bit in the secondary status register. the bridge also conditionally asserts p_serr# for any of the following reasons:
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 62 of 112 july 2004 revision 1.00 ! target abort detected during posted write transaction. ! master abort detected during posted write transaction. ! posted write data discarded after 2 24 (default) attempts to deliver (2 24 target retries received). ! parity error reported on target bus during po sted write transaction (see previous section) ! delayed write data discarded after 2 24 (default) attempts to deliver (2 24 target retries received) ! delayed read data cannot be tr ansferred from target after 2 24 (default) attempts (2 24 target retries received) ! master timeout on delayed transaction the device-specific p_serr# status register reports the reason for the assertion of p_serr#. most of these events have additional device-specific di sable bits in the p_serr# event disable register that make it possible to mask out p_serr# asse rtion for specific events. the master timeout condition has a serr# enable bit for that event in the bridge control register and therefore does not have a device-specific disable bit. 6 exclusive access this chapter describes the use of the lock# signa l to implement exclusive access to a target for transactions that cross the bridge. 6.1 concurrent locks the primary and secondary bus lo ck mechanisms operate concu rrently except when a locked transaction crosses the bridge. a primary master can lock a primar y target without affecting the status of the lock on the secondary bus, and vice ve rsa. this means that a primary master can lock a primary target at the same time that a secondary master lock s a secondary target. 6.2 acquiring exclusive access across pi7c8154a for any pci bus, before acquiring access to the lo ck# signal and starting a series of locked transactions, the initiator must first check that both of the following conditions are met: ! the pci bus must be idle. ! the lock# signal must be de-asserted. the initiator leaves the lock# signal de-asserted during the address phase and asserts lock# one clock cycle later. once a data transfer is comple ted from the target, the target lock has been achieved. 6.2.1 locked transactions in downstream direction locked transactions can cross the bridge only in the downstream direction, from the primary bus to the secondary bus. when the target resides on another pci bus, the master must acquire not only the lock on its own pci bus but also the lock on every bus between its bus and the target?s bus. when the bridge detects on the primary bus, an initial locked transaction intended for a target on the secondary bus,
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 63 of 112 july 2004 revision 1.00 the bridge samples the address, transaction type, byte enable bits, and parity, as described in section 2.7.4. it also samples the lock signal. if there is a lock established between 2 ports or the target bus is already locked by another master, then the current lock cycle is retried without forward. because a target retry is signaled to the initiator, the initiator must relinquish the lock on the primary bus, and therefore th e lock is not yet established. the first locked transaction must be a memory read transaction. subsequent locked transactions can be memory read or memory write transactions. post ed memory write transactions that are a part of the locked transaction sequence are still posted. memo ry read transactions that are a part of the locked transaction sequence are not pre-fetched. when the locked delayed memory read request is queued, the bridge do es not queue any more transactions until the locked sequence is finish ed. the bridge signals a target retry to all transactions initiated subsequent to the locked read transaction that are intended for targets on the other side of the bridge. the bridge allows any transactions queued before the locked transaction to complete before initiating the locked transaction. when the locked delayed memory read request transaction moves to the head of the delayed transaction queue, the bridge initiates the transac tion as a locked read transaction by de-asserting lock# on the target bus during the first address phase, and by asserting lock# one cycle later. if lock# is already asserted (used by another initiator), pi7c8 154a waits to request access to the secondary bus until lock# is de-asserted when the target bus is idle. note that the existing lock on the target bus could not have crossed pi7c8154a. otherwise, the pending queued locked transaction would not have been queued. when pi7c8154a is able to complete a data transfer with the locked read trans action, the lock is established on the secondary bus. when the initiator repeats the locked read trans action on the primary bus with the same address, transaction type, and byte enable bits, pi7c8154a tr ansfers the read data back to the initiator, and the lock is then also established on the primary bus. for pi7c8154a to recognize and respond to the initiator, the initiator?s subsequent attempts of the read transaction must use the locked transaction sequence (de-assert lock# during address phase, and assert lock# one cycle later). if the lock# se quence is not used in subsequent attempts, a master timeout condition may result. when a master timeout condition occurs, serr# is conditionally asserted (see section 5.4), the read data and queued read transaction are discarded, and the lock# signal is de-asserted on the target bus. once the intended target has been locked, any subsequent locked transactions initiated on the initiator bus that are forwarded by the bridge are dr iven as locked transactions on the target bus. the first transaction to establish lock# must be memory read. if the first transaction is not memory read, the following tran sactions behave accordingly: ! type 0 configuration read/wr ite induces master abort. ! type 1 configuration read/wr ite induces master abort. ! i/o read induces master abort. ! i/o write induces master abort. ! memory write induces master abort. when the bridge receives a target abort or a master abort in response to the delayed locked read transaction, this status is passed back to the in itiator, and no locks are established on either the target or the initiator bus. the bridge resumes forwarding unlocked transactions in both directions.
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 64 of 112 july 2004 revision 1.00 6.2.2 locked transaction in upstream direction the bridge ignores upstream lock and transacti ons. the bridge will pass these transactions as normal transactions without lock established. 6.3 ending exclusive access after the lock has been acquired on both initiator and target buses, the bridge must maintain the lock on the target bus for any subsequent locked transactions until the initiator relinquishes the lock. the only time a target-retry causes the lock to be relinquished is on the first transaction of a locked sequence. on subsequent transactions in the sequence, the target retry has no effect on the status of the lock signal. an established target lock is maintained until the initiator relinquishes the lock. the bridge does not know whether the current transaction is the la st one in a sequence of locked transactions until the initiator de-asserts the lock# signal at end of the transaction. when the last locked transaction is a delayed tr ansaction, the bridge has already completed the transaction on the target bus. in this example, as soon as the bridge detects that the initiator has relinquished the lock# signal by sampling it in the de-asserted state while frame# is de- asserted, the bridge de-asserts the lock# signal on the target bus as soon as possible. because of this behavior, lock# may not be de-asserted until se veral cycles after the last locked transaction has been completed on the target bus. as soon as the bridge has de-asserted lock# to indicate the end of a sequence of locked transactions, it resumes forwarding unlocked transactions. when the last locked transaction is a posted write transaction, the bridge de-asserts lock# on the target bus at the end of the tran saction because the lock was relin quished at the end of the write transaction on the initiator bus. when the bridge receives a target abort or a ma ster abort in response to a locked delayed transaction, the bridge returns a target abort or a master abort when the initi ator repeats the locked transaction. the initiator must then de-assert lock# at the end of the transaction. the bridge sets the appropriate status bits, flagging the abnormal target termination condition (see section 2.11). normal forwarding of unlocked posted and delayed transactions is resumed. when pi7c8154a receives a target abort or a master abort in response to a locked posted write transaction, pi7c8154a cannot pass back that stat us to the initiator. pi7c8154a asserts serr# on the initiator bus when a target abort or a master abort is received during a locked posted write transaction, if the serr# enable bit is set in the command register. signal serr# is asserted for the master abort condition if the master abort mode bit is set in the bridge control register (see section 5.4). 7 pci bus arbitration the bridge must arbitrate for use of the primary bus when forwarding upstream transactions. also, it must arbitrate for use of th e secondary bus when forwarding downstream transactions. the arbiter for the primary bus resides external to the bridge, typically on the motherboard. for the
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 65 of 112 july 2004 revision 1.00 secondary pci bus, the bridge implements an internal arbiter. this arbiter can be disabled, and an external arbiter can be used instead. this chapte r describes primary and secondary bus arbitration. 7.1 primary pci bus arbitration the bridge implements a request output pin, p_req#, and a grant input pin, p_gnt#, for primary pci bus arbitration. the bridge asserts p_req# wh en forwarding transactions upstream; that is, it acts as initiator on the primary pci bus. as long as at least one pending transaction resides in the queues in the upstream direction, either posted write data or delayed tr ansaction requests, the bridge keeps p_req# asserted. however, if a target retry, target disconnect, or a target abort is received in response to a transaction initiated by th e bridge on the primary pci bus, the bridge de- asserts p_req# for tw o pci clock cycles. for all cycles through the bridge, p_req# is not asserted until the transaction request has been completely queued. when p_gnt# is asserted low by the primary bus arbiter after the bridge has asserted p_req#, pi7c8154a initiates a trans action on the primary bus during the next pci clock cycle. when p_gnt# is a sserted to pi7c8154a when p_req# is not asserted, the bridge parks p_ad, p_cbe, and p_par by driving them to valid logic levels. when the primary bus is parked at the bridge and the bridge has a transacti on to initiate on the primary bus, the bridge starts the transaction if p_gnt# was asse rted during the previous cycle. 7.2 secondary pci bus arbitration the bridge implements an internal secondary pci bus arbiter. this arbiter supports eight external masters on the secondary bus in addition to pi7c8154a. the internal arbiter can be disabled, and an external arbiter can be used in stead for secondary bus arbitration. 7.2.1 secondary bus arbitration using the internal arbiter to use the internal arbiter, th e secondary bus arbiter enable pin, s_cfn#, must be tied low. pi7c8154a has nine secondary bus request input pins, s_req#[8:0], and has nine secondary bus output grant pins, s_gnt#[8:0], to support external secondary bus masters. the secondary bus request and grant signals are co nnected internally to the arbiter and are not brought out to external pins when s_cfn# is low. the secondary arbiter supports a 2-sets programmable 2-level rotating algorithm with each set taking care of 4 requests / grants. each set of masters can be assigned to a high priority group and a low priority group. the low priority group as a whole represents one entry in the high priority group; that is, if the high priority group consists of n masters, then in at least every n+1 transactions the highest priority is assigned to the low priority group. priority rotates evenly among the low priority group. therefore, members of the high priority group can be serviced n transactions out of n+1, while one member of the low priority group is serviced once every n+1 transactions. figure 7-1 shows an example of an internal arbiter wher e four masters, includi ng the bridge, are in the high priority group, and five masters are in th e low priority group. using this example, if all requests are always asserted, the highest priority rotates among the masters in the following fashion (high priority members are given in italics, low priority members, in boldface type): b, m0, m1, m2, m3 , b, m0, m1, m2, m4 , b, m0, m1, m2, m5 , b, m0, m1, m2, m6 and so on.
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 66 of 112 july 2004 revision 1.00 figure 7-1 secondary arbiter example each bus master, including pi7c8154a, can be configured to be in either the low priority group or the high priority group by setting the correspondin g priority bit in the arbiter-control register. the arbiter-control register is located at offset 40h. each master has a corresponding bit. if the bit is set to 1, the master is assigned to the high priority group. if the bit is set to 0, the master is assigned to the low priority group. if all the masters are a ssigned to one group, the algorithm defaults to a straight rotating priority among all the masters. afte r reset, all external mast ers are assigned to the low priority group, and pi7c8154a is assigned to the high priority group. pi7c8154a receives highest priority on the target bus every other transaction and priority rotates evenly among the other masters. priorities are re-evaluated every time s_frame# is asserted at the start of each new transaction on the secondary pci bus. from this point until the time that the next transaction starts, the arbiter asserts the grant signal corresponding to the highest priority request that is asserted. if a grant for a particular request is asserted, and a higher prior ity request subsequently asserts, the arbiter de- asserts the asserted grant signal and asserts the grant corresponding to the new higher priority request on the next pci clock cycle. when prio rities are re-evaluated, the highest priority is assigned to the next highest priority master relative to the master that initiated the previous transaction. the master that initiated the last tran saction now has the lowest priority in its group. if pi7c8154a detects that an initiator has failed to assert s_frame# after 16 cycles of both grant assertion and a secondary idle bus conditio n, the arbiter de-asserts the grant. to prevent bus contention, if the secondary pci bus is idle, the arbiter never asserts one grant signal in the same pci cycle in which it de-asserts another. it de-asserts one grant and asserts the next grant, no earlier than one pci clock cycle la ter. if the secondary pci bus is busy, that is, s_frame# or s_irdy# is asserted , the arbiter can be de-asserted one grant and asserted another grant during the same pci clock cycle. 7.2.2 preemption preemption can be programmed to be either on or off, with the default to on (offset 4ch, bit 31=0). time-to-preempt can be programmed to 0, 1, 2, 4, 8, 16, 32, or 64 (default is 0) clocks. if the current master occupies the bus and other masters are waiting, the current master will be preempted by removing its grant (gnt#) after the ne xt master waits for the time-to-preempt. m1 m2 m0 m3 m4 m6 m7 m8 b lpg m5 lpg: low priority group b: pi7c8154a mx: bus master
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 67 of 112 july 2004 revision 1.00 7.2.3 secondary bus arbitration using an external arbiter the internal arbiter is disabled when the secondary bus central function control pin, s_cfn#, is tied high. an external arbiter must then be used. when s_cfn# is tied high, pi7c8154a reconfigures two pins to be external request and grant pins. the s_gnt#[0] pin is reconfigured to be the external request pin because it?s an output. the s_req#[0] pin is reconfigured to be the external grant pin because it?s an input. wh en an external arbiter is used, pi7c8154a uses the s_gnt#[0] pin to request the secondary bus. when the reconfigured s_req#[0] pin is asserted low after pi7c8154a has asserted s_gnt#[0], pi7c8154a initiates a transaction on the secondary bus one cycle later. if grant is asserted and pi7c8154a has not asserted the request, pi7c8154a parks ad, cbe and par pins by driving them to valid logic levels. the unused secondary bus grant outputs, s_gnt#[8:1] are driven high. the unused secondary bus request inputs, s_req#[8:1], should be pulled high. 7.2.4 bus parking bus parking refers to driving the ad[31:0], cbe[3:0], and par lines to a known value while the bus is idle. in general, the device implementing the bus arbiter is responsible for parking the bus or assigning another device to park the bus. a device parks the bus when the bus is idle, its bus grant is asserted, and the device?s request is not asserted. the ad[31:0] and cbe[3:0] signals should be driven first, with the par signal driven one cycle later. the ad[63:32] and cbe[7:4] are not driven and need to be pulled up to a valid logic level through external resistors. pi7c8154a parks the primary bus only when p_gnt# is asserted, p_req# is de-asserted, and the primary pci bus is idle. when p_gnt# is de-asserted, pi7c8154a 3-states the p_ad, p_cbe, and p_par signals on the next pci clock cycle. if pi7c8154a is parking the primary pci bus and wants to initiate a transaction on that bus, then pi7c8154a can start the transaction on the next pci clock cycle by asserting p_frame# if p_gnt# is still asserted. if the internal secondary bus arbiter is enabled, the secondary bus is always parked at the last master that used the pci bus. that is, pi7c81 54a keeps the secondary bu s grant asserted to a particular master until a new secondary bus request comes along. after reset, pi7c8154a parks the secondary bus at itself until transactions start occurr ing on the secondary bus. offset 48h, bit 1, can be set to 1 to park the secondary bus at pi7c8154a. by default, offset 48h, bit 1, is set to 0. if the internal arbiter is disabled, pi7c8154a parks the secondary bus only when the reconfigured grant signal, s_req#[0], is asserted and the secondary bus is idle. 8 general purpose i/o interface the pi7c8154a implements a 4-pin general purp ose i/o interface. during normal operation, device specific configuration regist ers control the gpio interface. the gpio interface can be used for the following functions: ! during secondary interface reset, the gpio interf ace can be used to shift in a 16-bit serial stream that serves as a secondary bus clock disable mask. ! along with the gpio[3] pin, a live insertion bit can be used to bring the pi7c8154a to a halt through hardware, permitting live insertion of option cards behind the pi7c8154a.
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 68 of 112 july 2004 revision 1.00 8.1 gpio control registers during normal operation, the fo llowing device specific configura tion registers control the gpio interface: ! the gpio output data register ! the gpio output enable control register ! the gpio input data register these registers consist of five 4-bit fields: ! write-1-to-set output data field ! write-1-to-clear output data field ! write-1-to-set signal output enable control field ! write-1-to-clear signal out put enable control field ! input data field the bottom four bits of the output enable fields control whether each gpio signal is input only or bi-directional. each signal is controlled independently by a bit in each output enable control field. if a 1 is written to the write-1-to-set field, the corresponding pin is activated as an output. if a 1 is written to the write-1-to-clear field, the output driver is tri-stated, and the pin is then input only. writing zeroes to these register s has no effect. the reset for these signals is input only. the input data field is read only and reflects th e current value of the gpio pins. a type 0 configuration read operation to this address is used to obtain the values of these pins. all pins can be read at any time, whether configured as input only or as bi-directional. the output data fields also use the write-1-to-set and write-1-to-clear mode. if a 1 is written to the write-1-to-set field and the pin is enabled as an output, the corresponding gpio output is driven high. if a 1 is written to the write-1-to-clear field and the pin is enabled as an output, the corresponding gpio output is dr iven low. writing zeros to these registers has no effect. the value written to the output register will be driven only when the gpio signal is configured as bi- directional. a type 0 configuration write operation is used to program these fields. the rest value for the output is 0. 8.2 secondary clock control the pi7c8154a uses the gpio pins and the msk_in signal to input a 16-bit serial data stream. this data stream is shifted into the secondary cl ock control register and is used for selectively disabling secondary clock outputs. the serial data stream is shifted in as soon as p_reset# is detected deas serted and the secondary reset signal, s_reset#, is detected asserted. the deassertion of s_reset# is delayed until the pi7c8154a completes shifting in the clock mask data, which takes 23 clock cycles. after that, the gpio pins can be used as general-purpose i/o pins. an external shift register should be used to load and shift the data. the gpio pins are used for shift register control and serial data input. table 8-1 shows the operation of the gpio pins.
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 69 of 112 july 2004 revision 1.00 table 8-1 gpio operation gpio pin operation gpio[0] shift register clock output at 33mhz max frequency gpio[1] not used gpio[2] shift register control 0: load 1: shift gpio[3] not used the data is input through the dedicated input signal, msk_in. the shift register circuitry is not necessary for co rrect operation of pi7c815 4a. the shift register can be eliminated, and msk_in can be tied low to enable all secondary clock outputs or tied high to force all secondary clock outputs high. table 8-2 shows the format of the serial stream. table 8-2 gpio serial data format bit description s_clkout [1:0] slot 0 prsnt#[1:0] or device 0 0 [3:2] slot 1 prsnt#[1:0] or device 1 1 [5:4] slot 2 prsnt#[1:0] or device 2 2 [7:6] slot 3 prsnt#[1:0] or device 3 3 [8] device 4 4 [9] device 5 5 [10] device 6 6 [11] device 7 7 [12] device 8 8 [13] pi7c8154a s_clkin 9 [14] reserved na [15] reserved na the first 8 bits contain the prsnt#[1:0] signal va lues for four slots, and these bits control the s_clkout[3:0] outputs. if one or both of the pr snt#[1:0] signals are 0, that indicates that a card is present in the slot and th erefore the secondary clock for that slot is not masked. if these clocks are connected to devices and not to slots, one or both of the bits should be tied low to enable the clock. the next 5 bits are the clock mask for devices; each bit enables or disables the clock for one device. these bits control the s_clkout[8:4] outputs: 0 en ables the clock, and 1 disables the clock. bit 13 is the clock enable bit for s_clkout[9], which is connected to pi7c8154a?s s_clkin input. if desired, the assignment of s_clkout outputs to slots, devices, and pi7c8154a?s s_clkin input can be rearranged from the assignment shown here. however, it is important that the serial data stream format match the assignment of s_clkout. the 8 least significant bits are co nnected to the prsnt# pins for the slots. the next 5 bits are tied high to disable their respective secondary cloc ks because those clocks are not connected to anything. the next bit is tied low because that secondary clock outp ut is connected to the bridge s_clkin input. when the secondary reset signal, s_ reset#, is detected asserted and the primary reset signal, p_reset#, is detected deasserted, the bridge drives gpio[2] low for one cycle to load the clock mask inputs into the shift register . on the next cycle, pi 7c8154a drives gpio[2] high to perform a shift operation. this shifts the clock mask into msk_in; the most significant bit is shifted in first, and the least significant bit is shifted in last.
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 70 of 112 july 2004 revision 1.00 after the shift operation is complete, the bridge tri-states the gpio signals and deasserts s_reset#. pi7c8154a then ignores msk_in. control of the gpio signal now reverts to pi7c8154a gpio control registers. the clock disable mask can be modified subsequently through a configuration write command to the secondary clock control register in device-specific configuration space. 8.3 live insertion the gpio[3] pin can be used, along with a live insertion mode bit, to disable transaction forwarding. to enable live insertion mode, the live insertion mode bit in the chip control register must be set to 1, and the output enable control for gpio[3] must be set to input only in the gpio output enable control register. when live insertion mode is enable d, whenever gpio[3] is driven to a value of 1, the i/o enable, the memory enable, and the master enable bits are internally masked to 0. this means that, as a target, pi7c8154a no longer accept s any i/o or memory transactions, on either interface. when read, the register bits still reflect the value originally written by a configuration write command; when gpio[3] is deasserted, the intern al enable bits return to their original value (as they appear when read from the command regist er). when this mode is enabled, as a master, pi7c8154a completes any posted write or delayed request transactions that have already been queued. delayed completion transactions are not returned to the master in this mode because the bridge is not responding to any i/o or memory transactions during this time. pi7c8154a continues to accept type 0 configuration transac tions in live insertion mode. on ce live insertion mode brings the bridge to a halt and queued transactions are co mpleted, the secondary reset bit in the bridge control register can be used to assert s_reset#, if desired, to reset and tri-state secondary bus devices, and to enable any live insertion hardware. 9 eeprom interface the eeprom interface consists of three pins: eeclk (eeprom clock output), eepd (eeprom bi-directional serial data), and ee_en# (eeprom enable on a low input). the bridge may control an issi is24c02 or compatible part, which is organized into 256x8 bits. the eeprom is used to initialize a select number of re gisters. this is accomplished after p_reset# is deasserted, at which time the data from th e eeprom will be loaded. the eeprom interface is organized into a 16-bit base, and the bridge supp lies a 7-bit eeprom word address. the bridge does not control the eeprom address input. it can only access the eeprom with address input set to 0. 9.1 auto mode eeprom access the bridge may access the eeprom in a word fo rmat by utilizing the auto mode through a hardware sequencer. the eeprom start contro l, address, and read/write commands can be accessed through the configuration register. befo re each access, the software should check the start eeprom bit before issuing the next start.
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 71 of 112 july 2004 revision 1.00 9.2 eeprom mode at reset during a reset, the bridge will autoload information/data from the eeprom if the automatic load condition is met. the first offset in the eepro m contains a signature. if the signature is recognized, the autoload will initiate right after the reset. during the autoload, the bridge will read sequential words from the eeprom and write to the appropriate registers. before th e bridge registers can be accessed through the host, the autoload condition should be verified by reading bit[3] offset 54h (eeprom autoload status). the host access is allowed only after the status of this b it becomes '1' which signif ies that the autoload initialization sequence has completed successfully. 9.3 eeprom data structure the bridge will access the eeprom one word at a time. the bit order during the address phase is reverse that of the data phase. the data order starts with the msb to the lsb during the address phase, but starts with the lsb to the msb during the data phase. 9.4 eeprom content eeprom byte address configuration offset description 00 ? 01h eeprom signature autoload will only proceed if it reads a value of 1516h on the first word loaded. 02h region enable enables or disables certain regions of the pci configuration space from being loaded with contents in the eeprom. bit[0]: reserved bit[4:1]: 0000 = stop autoload at offset 03h 0001 = stop autoload at offset 0fh 0011 = stop autoload at offset 2bh other combinations are undefined bit[7:5]: reserved 03h enable miscellaneous functions bit[0]: isa enable control bit write protect ? when this it is set, bridge will change bit[2] offset 3eh into read only, and the isa enable feature will not be available. 04 ? 05h 00 ? 01h vendor id 06 ? 07h 02 ? 03h device id 08h reserved 09h 09h class code ? low byte of class code register 0a ? 0bh 0a ? 0bh class code ? uppe r bytes of class code register 0ch 0eh header type 0dh 0fh bist 0e ? 0fh reserved 10 ? 11h 42 ? 43h arbiter control register 12h 48h memory read flow/underflow control 13h 4ah upstream memory base and limit enable 14h 4fh arbiter pre-emption control (only bit[31:28]) 15 ? 16h 58 ? 59h upstream memory base register 17 ? 18h 5a ? 5bh upstream memory limit register 19 ? 1ch 5c ? 5fh upstream memo ry base upper 32-bit register 1d ? 20h 60 ? 63h upstream memory limit upper 32-bit register
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 72 of 112 july 2004 revision 1.00 eeprom byte address configuration offset description 21 ? 22h 74 ? 75h port option register 23 ? 24h 80 ? 81h secondary master timeout counter 25 ? 26h 82 ? 83h primary master timeout counter 27 ? 28h de ? dfh power management capabilities 29 ? 2ah e0 ? e1h power manageme nt control status register 2bh e3h power management data 2c ? 3fh reserved ? must be set to 0 10 vital product data (vpd) the bridge contains the vital product data registers as specified in the pci local bus specification, revision 2.2. the bridge provides 192 bytes of storage in the eeprom for the vpd data starting at offset ech of the configuration space. 11 clocks this chapter provides information about the clocks. 11.1 primary and secondary clock inputs pi7c8154a implements a primary clock input fo r the pci interface. the primary interface is synchronized to the primary cloc k input, p_clk, and the secondar y interface is synchronized to the secondary clock input. the secondary clock op erates at either the same frequency as the primary clock or at half of the frequency of the primary clock. pi7c8154a operates at a maximum frequency of 66 mhz. 11.2 secondary clock outputs the bridge has 10 secondary clock outputs, s_clkout[9:0], that can be used as clock inputs for up to nine external secondary bus devices. the s_clkout[9:0] outputs are derived from p_clk. these are the rules for using secondary clocks: ! each secondary clock output is limited to no more than one load ! one of the secondary clock outputs must be used to feedback to s_clkin 12 pci power management pi7c8154a incorporates functionality that meets the requirements of the pci power management specificatio n, revision 1.0 . these features include: ! pci power management registers using the enhanced capabilities port (ecp) address mechanism ! support for d0, d3 hot and d3 cold power management states
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 73 of 112 july 2004 revision 1.00 ! support for d0, d1, d2, d3 hot , and d3 cold power management states for devices behind the bridge ! support of the b2 secondary bus power state when in the d3 hot power management state table 12-1 shows the states and related actions that the bridge performs during power management transitions. (no other transactions are permitted.) table 12-1 power management transitions current status next state action d0 d3 cold power has been removed from pi 7c8154a. a power-up reset must be performed to bring pi7c8154a to d0. d0 d3 hot if enabled to do so by the bpcce pin, pi7c8154a will disable the secondary clocks and drive them low. d0 d2 unimplemented. pi7c8154a will ignore the write to the power state bits. power state will remain at d0. d0 d1 unimplemented. pi7c8154a will ignore the write to the power state bits. power state will remain at d0. d3 hot d0 pi7c8154a enables secondary clock outputs and performs an internal chip reset. signal s_rst# will not be asserted. all registers will be returned to the reset values and buffers will be cleared. d3 cold d3 cold power has been removed from pi7c8154a. a power-up reset must be performed to bring pi7c8154a to d0. d3 cold d0 power-up reset. pi7c8154a pe rforms the standard power-up reset functions as described in section 11. pme# signals are routed fr om downstream devices around pci-to-pci bridges. pme# signals do not pass through pci-to-pci bridges.
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 74 of 112 july 2004 revision 1.00 13 reset this chapter describes the primary interface, s econdary interface, and chip reset mechanisms. 13.1 primary interface reset pi7c8154a has a reset input, p_reset#. when p_ reset# is asserted, the following events occur: ! pi7c8154a immediately tri-stat es all primary pci interface signals. s_ad[31:0] and s_cbe[3:0] are driven low on th e secondary interface and other control signals are tri-stated. ! pi7c8154a performs a chip reset. ! registers that have default values are reset. ! pi7c8154a samples p_req64# to determine whether the 64-bit extension is enabled on the primary. p_reset# asserting and de-asserting edges can be asynchronous to p_clk and s_clkout. pi7c8154a is not accessible during p_reset#. after p_reset# is de-asserted, pi7c8154a remains inaccessible for 16 pci clocks before the first configuration transaction can be accepted. 13.2 secondary interface reset the bridge is responsible for driving the secondary bus reset signals, s_reset#. bridge asserts s_reset# when any of the following conditions are met: signal p_reset# is asserted. signal s_reset# remains asserted as long as p_reset# is asserted and does not de-assert until p_reset# is de-asserted. the secondary reset bit in the bridge control register is set. signal s_reset# remains asserted until a configuration write operation clears the secondary reset bit. the chip reset bit in the diagno stic control register is set. s_reset# remains asserted until a configuration write operation clears the secondary re set bit. the s_reset# in asserting and de- asserting edges can be asynchronous to p_clk. when s_reset# is asserted, all secondary pci in terface control signals, including the secondary grant outputs, are immediately tri- stated. signals s_ad[31 :0], s_cbe[3:0], s_par are driven low for the duration of s_reset# assertion. s_req64# is asserted low to indicate 64-bit extension support on the secondary. all posted write an d delayed transaction da ta buffers are reset. therefore, any transactions residing inside the buffers at the time of secondary reset are discarded. when s_reset# is asserted by means of the secondary reset bit, pi 7c8154a remains accessible during secondary interface reset and continues to respond to accesses to its configuration space from the primary interface.
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 75 of 112 july 2004 revision 1.00 13.3 chip reset the chip reset bit in the diagnostic control regi ster can be used to reset the pi7c8154a and the secondary bus. when the chip reset bit is set, all registers and ch ip state are reset and all signals are tri-stated. s_reset# is asserted and the secondary reset bit is automatically set. s_reset# remains asserted until a configuration write operation clears the secondary reset bit. within 20 pci clock cycles after completion of the configuration write operation, pi7c8154a?s reset bit automatically clears and pi7c8154a is ready for configuration. during reset, pi7c8154a is inaccessible.
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 76 of 112 july 2004 revision 1.00 14 configuration registers pci configuration defines a 64 dword space to define various attributes of pi7c8154a as shown below. table 14-1 configuration space map 31-24 23-16 15-8 7-0 dword address device id vendor id 00h primary status command 04h class code revision id 08h reserved header type primary latency timer cache line size 0ch reserved 10h reserved 14h secondary latency timer subordinate bus number secondary bus number primary bus number 18h secondary status i/o limit a ddress i/o base address 1ch memory limit address memory base address 20h prefetchable memory limit address prefetchable memory base address 24h prefetchable memory base address upper 32-bit 28h prefetchable memory limit address upper 32-bit 2ch i/o limit address upper 16-bit i/ o base address upper 16-bit 30h reserved capability pointer 34h reserved 38h bridge control interrupt pin (not supported) interrupt line (not supported) 3ch arbiter control diagnostic / chip control 40h reserved 44h upstream memory control extended chip control 48h secondary bus arbiter preemptio n control hot swap switch time slot 4ch eeprom autoload control/status reserved 50h eeprom data eeprom address/control 54h upstream (s to p) memory limit upstream (s to p) memory base 58h upstream (s to p) memory base upper 32-bit 5ch upstream (s to p) memory limit upper 32-bit 60h gpio data and control p_serr# event disable 64h reserved p_serr# status secondary clock control 68h reserved 6ch - 70h reserved port option 74h reserved 78h reserved 7ch primary master timeout counter s econdary master timeout counter 80h reserved 84h ? ach chassis number slot number next pointer capability id b0h reserved b4h ? bfh c0h - cfh reserved d0h ?d8h power management capabilities next item pointer capability id dch data ppb support extensions power management data e0h hot swap control and status next item pointer capability id e4h vpd next item pointer capability id e8h vpd data ech
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 77 of 112 july 2004 revision 1.00 14.1.1 signal types signal type description r/o read only r/w read / write r/wc read / write 1 to clear r/wr read / write 1 to reset (about 20 clocks) r/ws read / write 1 to set 14.1.2 vendor id register ? offset 00h bit function type description 15:0 vendor id r/o identifies pericom as vendor of this device. hardwired as 12d8h. 14.1.3 device id register ? offset 00h bit function type description 31:16 device id r/o identifies this device as the pi7c8154a. hardwired as 8154h. 14.1.4 command register ? offset 04h bit function type description 0 i/o space enable r/w controls response to i/o access on the primary interface 0: ignore i/o transactions on the primary interface 1: enable response to i/o tran sactions on the primary interface reset to 0 1 memory space enable r/w controls response to memory accesses on the primary interface 0: ignore memory transactions on the primary interface 1: enable response to memory tr ansactions on the primary interface reset to 0 2 bus master enable r/w controls ability to operate as a bus master on the primary interface 0: do not initiate memory or i/o transactions on the primary interface and disable response to memory and i/o transactions on the secondary interface 1: enables bridge to operate as a master on the primary interfaces for memory and i/o transactions forw arded from the secondary interface reset to 0 3 special cycle enable r/o no special cycles defined. bit is defined as read only and returns 0 when read 4 memory write and invalidate enable r/o bridge does not generate memory wr ite and invalidate except forwarding a transaction for another master. bi t is implemented as read only and returns 0 when read.
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 78 of 112 july 2004 revision 1.00 bit function type description 5 vga palette snoop enable r/w controls response to vga compatible palette accesses 0: ignore vga palette accesses on the primary 1: enable positive decoding response to vga palette writes on the primary interface with i/o address bits ad[9:0] equal to 3c6h, 3c8h, and 3c9h (inclusive of isa alias; ad[15: 10] are not decoded and may be any value) 6 parity error response r/w controls response to parity errors 0: bridge may ignore any parity errors that it detects and continue normal operation 1: bridge must take its normal acti on when a parity error is detected reset to 0 7 wait cycle control r/o controls the ability to perform address / data stepping 0: disable address/data steppi ng (affects primary and secondary) reset to 0 8 p_serr# enable r/w controls the enable for the p_serr# pin 0: disable the p_serr# driver 1: enable the p_serr# driver reset to 0 9 fast back-to- back enable r/w controls bridge?s ability to generate fast back-to-back transactions to different devices on the primary interface. 0: no fast back-to-back transactions 1: enable fast back-t o-back transactions reset to 0 15:10 reserved r/o returns 000000 when read 14.1.5 status register ? offest 04h bit function type description 19:16 reserved r/o reset to 0 20 capabilities list r/o set to 1 to enable support for the capability list (offset 34h is the pointer to the data structure) reset to 1 21 66mhz capable r/o set to 1 to enable 66mhz operation on the primary interface reset to 1 22 reserved r/o reset to 0 23 fast back-to- back capable r/o set to 1 to indicate bridge is cap able of decoding fast back-to-back transactions on the primary interface to different targets reset to 1 24 data parity error detected r/wc 0: no parity error detected on th e primary interface (bridge is the primary bus master) 1: parity error detected on the pr imary interface (bridge is the primary bus master) reset to 0 26:25 devsel# timing r/o devsel# timing (medium decoding) 01: medium devsel# decoding reset to 01
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 79 of 112 july 2004 revision 1.00 bit function type description 27 signaled target abort r/wc 0: bridge does not signal ta rget abort on the primary interface 1: bridge signals target abort on the primary interface reset to 0 28 received target abort r/wc 0: bridge does not detect target abort on the primary interface 1: bridge detects target abort on the primary interface reset to 0 29 received master abort r/wc 0: bridge does not detect master abort on the primary interface 1: bridge detects master abort on the primary interface reset to 0 30 signaled system error r/wc 0: bridge does not assert serr# on the primary interface 1: bridge asserts serr# on the primary interface reset to 0 31 detected parity error r/wc 0: address of data parity error not detected by the bridge on the primary interface 1: address of data parity error de tected by the bridge on the primary interface reset to 0 14.1.6 revision id register ? offset 08h bit function type description 7:0 revision r/o indicates revision nu mber of device. hardwired to 02h 14.1.7 class code register ? offset 08h bit function type description 15:8 programming interface r/o read as 0 to indicate no programming interfaces have been defined for pci-to-pci bridges 23:16 sub-class code r/o read as 04h to indicate device is pci-to-pci bridge 31:24 base class code r/o read as 06h to indicate device is a bridge device 14.1.8 cache line size register ? offset 0ch bit function type description 7:0 cache line size r/w designates the cache line size for the system and is used when terminating memory write and i nvalidate transactions and when prefetching memory read transactions. only cache line sizes (in units of 4- byte) which are a power of two are valid (only one bit can be set in this register; only 00h, 01h, 02h, 04h, 08h, and 10h are valid values). reset to 0 14.1.9 primary latency timer register ? offset 0ch bit function type description 15:8 primary latency timer r/w this register sets the value for th e master latency timer, which starts counting when the master asserts frame#. reset to 0
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 80 of 112 july 2004 revision 1.00 14.1.10 header type register ? offset 0ch bit function type description 23:16 header type r/o read as 01h to indicate that the register layout conf orms to the standard pci-to-pci bridge layout. 14.1.11 primary bus number register ? offset 18h bit function type description 7:0 primary bus number r/w indicates the number of the pci bus to which the primary interface is connected. the value is set in software during configuration. reset to 0 14.1.12 secondary bus number register ? offset 18h bit function type description 15:8 secondary bus number r/w indicates the number of the pci bus to which the secondary interface is connected. the value is set in software during configuration. reset to 0 14.1.13 subordinate bus number register ? offset 18h bit function type description 23:16 subordinate bus number r/w indicates the number of the pci bus with the highest number that is subordinate to the bridge. the value is set in software during configuration. reset to 0 14.1.14 secondary latency timer ? offset 18h bit function type description 31:24 secondary latency timer r/w designated in units of pci bus cloc ks. latency timer checks for master accesses on the secondary bus interfaces that remain unclaimed by any target. reset to 0 14.1.15 i/o base register ? offset 1ch bit function type description 1:0 32-bit indicator r/o read as 01h to indicate 32-bit i/o addressing 3:2 reserved r/o returns 00 when read. reset to 00.
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 81 of 112 july 2004 revision 1.00 bit function type description 7:4 i/o base address [15:12] r/w defines the bottom address of the i/o address range for the bridge to determine when to forward i/o tran sactions from one interface to the other. the upper 4 bits correspond to address bits [15:12] and are writable. the lower 12 bits corresponding to address bits [11:0] are assumed to be 0. the upper 16 bits corresponding to address bits [31:16] are defined in the i/o base addr ess upper 16 bits address register reset to 0 14.1.16 i/o limit register ? offset 1ch bit function type description 9:8 32-bit indicator r/o read as 01h to indicate 32-bit i/o addressing 11:10 reserved r/o returns 00 when read. reset to 00 15:12 i/o limit address [15:12] r/w defines the top address of the i/ o address range for the bridge to determine when to forward i/o tran sactions from one interface to the other. the upper 4 bits correspond to address bits [15:12] and are writable. the lower 12 bits corresponding to address bits [11:0] are assumed to be fffh. the upper 16 bits corresponding to address bits [31:16] are defined in the i/o limit address upper 16 bits address register reset to 0 14.1.17 secondary status register ? offset 1ch bit function type description 20:16 reserved r/o reset to 0 21 66mhz capable r/o set to 1 to enable 66mhz operation on the secondary interface reset to 1 22 reserved r/o reset to 0 23 fast back-to- back capable r/o set to 1 to indicate bridge is capab le of decoding fast back-to-back transactions on the secondary interface to different targets reset to 1 24 data parity error detected r/wc set to 1 when s_perr# is asserted and bit 6 of command register is set reset to 0 26:25 devsel# timing r/o devsel# timing (medium decoding) 01: medium devsel# decoding reset to 01 27 signaled target abort r/wc set to 1 (by a target device) whenever a target abort cycle occurs on its secondary interface reset to 0 28 received target abort r/wc set to 1 (by a master device) when ever transactions on its secondary interface are terminated with target abort reset to 0 29 received master abort r/wc set to 1 (by a master) when transac tions on its secondary interface are terminated with master abort reset to 0 30 received system error r/wc set to 1 when s_serr# is asserted reset to 0
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 82 of 112 july 2004 revision 1.00 bit function type description 31 detected parity error r/wc set to 1 when address or data parity error is detected on the secondary interface reset to 0 14.1.18 memory base register ? offset 20h bit function type description 3:0 reserved r/o lower four bits of register are read only and return 0. reset to 0 15:4 memory base address [15:4] r/w defines the bottom address of an address range for the bridge to determine when to forward memory tr ansactions from one interface to the other. the upper 12 bits correspond to address bits [31:20] and are writable. the lower 20 bits corresponding to address bits [19:0] are assumed to be 0. reset to 0 14.1.19 memory limit register ? offset 20h bit function type description 19:16 reserved r/o lower four bits of register are read only and return 0. reset to 0 31:20 memory limit address [31:20] r/w defines the top address of an addr ess range for the bridge to determine when to forward memory transactions from one interface to the other. the upper 12 bits correspond to address bits [31:20] and are writable. the lower 20 bits corresponding to address bits [19:0] are assumed to be fffffh. 14.1.20 prefetchable memory base address register ? offset 24h bit function type description 3:0 64-bit addressing r/o indicates 64-bit addressing 0000: 32-bit addressing 0001: 64-bit addressing reset to 0001 15:4 prefetchable memory base address [31:20] r/w defines the bottom address of an address range for the bridge to determine when to forward memory read and write transactions from one interface to the other. the upper 12 bits correspond to address bits [31:20] and are writable. the lower 20 bits are assumed to be 0.
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 83 of 112 july 2004 revision 1.00 14.1.21 prefetchable memory limit address register ? offset 24h bit function type description 19:16 64-bit addressing r/o i ndicates 64-bit addressing 0000: 32-bit addressing 0001: 64-bit addressing reset to 1 31:20 prefetchable memory limit address [31:20] r/w defines the top address of an addr ess range for the bridge to determine when to forward memory read and wr ite transactions from one interface to the other. the upper 12 bits correspond to address bits [31:20] and are writable. the lower 20 bits are assumed to be fffffh. 14.1.22 prefetchable memory base address upper 32-bits register ? offset 28h bit function type description 31:0 prefetchable memory base address, upper 32-bits [63:32] r/w defines the upper 32-bits of a 64-b it bottom address of an address range for the bridge to determine when to forward memory read and write transactions from one interface to the other. reset to 0 14.1.23 prefetchable memory limit address upper 32-bits register ? offset 2ch bit function type description 31:0 prefetchable memory limit address, upper 32-bits [63:32] r/w defines the upper 32-bits of a 64-bit top address of an address range for the bridge to determine when to forward memory read and write transactions from one interface to the other. reset to 0 14.1.24 i/o base address upper 16-bits register ? offset 30h bit function type description 15:0 i/o base address, upper 16-bits [31:16] r/w defines the upper 16-bits of a 32-b it bottom address of an address range for the bridge to determine when to forward i/o transactions from one interface to the other. reset to 0 14.1.25 i/o limit address upper 16-bits register ? offset 30h bit function type description 31:16 i/o limit address, upper 16-bits [31:16] r/w defines the upper 16-bits of a 32-bit top address of an address range for the bridge to determine when to forward i/o transactions from one interface to the other. reset to 0
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 84 of 112 july 2004 revision 1.00 14.1.26 capability pointer register ? offset 34h bit function type description 7:0 enhanced capabilities port pointer r/o enhanced capabilities port offset point er. read as dch to indicate that the first item resides at that configuration offset. reset to dch. 14.1.27 interrupt line register ? offset 3ch bit function type description 7:0 interrupt line r/w for post to program to ffh, indicating that the bridge does not implement an interrupt pin. reset to 0. 14.1.28 interrupt pin register ? offset 3ch bit function type description 15:8 interrupt pin r/o interrupt pin not supported on the bridge. reset to 0. 14.1.29 bridge control register ? offset 3ch bit function type description 16 parity error response r/w controls the bridge?s response to pa rity errors on the secondary interface. 0: ignore address and data parity errors on the secondary interface 1: enable parity error reporting a nd detection on the secondary interface reset to 0 17 s_serr# enable r/w controls the forwar ding of s_serr# to the primary interface. 0: disable the forwarding of s_serr# to primary interface 1: enable the forwarding of s_serr# to primary interface reset to 0 18 isa enable r/w modifies the bridge?s response to isa i/o addresses, applying only to those addresses falling within the i/o base and limit address registers and within the first 64kb of pci i/o space. 0: forward all i/o addresses in the ra nge defined by the i/o base and i/o limit registers 1: blocks forwarding of isa i/o addre sses in the range defined by the i/o base and i/o limit registers that are in the first 64kb of i/o space that address the last 768 bytes in each 1kb block. secondary i/o transactions are forwarded upstream if the address falls within the last 768 bytes in each 1kb block reset to 0
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 85 of 112 july 2004 revision 1.00 bit function type description 19 vga enable r/w controls the bridge?s response to vga compatible addresses. 0: does not forward vga compatible memory and i/o addresses from primary to secondary 1: forward vga compatible memory and i/o addresses from primary to secondary regardless of other settings reset to 0 20 reserved r/o reserved. retu rns 0 when read. reset to 0 21 master abort mode r/w control?s bridge?s behavior res ponding to master aborts on secondary interface. 0: does not report master aborts (returns ffff_ffffh on reads and discards data on writes) 1: reports master aborts by signaling target abort if possible or by the assertion of p_serr# if enabled reset to 0 22 secondary interface reset r/w controls the assertion of s_reset# signal pin on the secondary interface 0: does not force the assertion of s_reset# pin 1: forces the assertion of s_reset# reset to 0 23 fast back-to- back enable r/w controls bridge?s ability to generate fast back-to-back transactions on the secondary interface. 0: does not allow fast back-to-back transactions on the secondary 1: enables fast back-to-back transactions on the secondary reset to 0 24 primary master timeout r/w determines the maximum number of pci clock cycles the bridge waits for an initiator on the primary interfac e to repeat a delayed transaction request. 0: primary discard timer counts 2 15 pci clock cycles. 1: primary discard timer counts 2 10 pci clock cycles. reset to 0 25 secondary master timeout r/w determines the maximum number of pci clock cycles the bridge waits for an initiator on the primary interfac e to repeat a delayed transaction request. 0: primary discard timer counts 2 15 pci clock cycles. 1: primary discard timer counts 2 10 pci clock cycles. reset to 0 26 master timeout status r/wc this bit is set to 1 when either the primary master timeout counter or secondary master timeout counter expires. reset to 0 27 discard timer p_serr# enable r/w this bit is set to 1 and p_serr# is asserted when either the primary discard timer or the secondary discard timer expire. 0: p_serr# is not asserted on the primary interface as a result of the expiration of either the primary disc ard timer or the secondary discard timer. 1: p_serr# is asserted on the prim ary interface as a result of the expiration of either the primary disc ard timer or the secondary discard timer. reset to 0
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 86 of 112 july 2004 revision 1.00 bit function type description 31-28 reserved r/o reserved. retu rns 0 when read. reset to 0. 14.1.30 diagnostic / chip control register ? offset 40h bit function type description 0 reserved r/o reserved. retu rns 0 when read. reset to 0 1 memory write disconnect control r/w controls when the bridge (as a target) disconnects memory write transactions. 0: memory write disconnects at 4kb aligned address boundary 1: memory write disconnects at cache line aligned address boundary reset to 0 3:2 reserved r/o reserved. retu rns 0 when read. reset to 0. 4 secondary bus prefetch disable r/w controls the bridge?s ability to prefetch duri ng upstream memory read transactions 0: bridge prefetches and does not forward byte enable bits during upstream memory read transactions. 1: bridge requests only 1 dword from the target and forwards read byte enable bits during upstream memory reads. reset to 0 5 live insertion mode r/w enables control of transaction forwarding 0: gpio[3] has no effect on the i/o, memory, and master enable bits 1: if gpio[3] is set to input only, this bit enables gpio[3] to mask the i/o enable, memory enable, and master enable bits to 0. these bits are masked when gpio[3] is driven high. as a result, pi7c8154 stops accepting i/o and memory transactions. reset to 0 7:6 reserved r/o reserved. retu rns 0 when read. reset to 0 8 chip reset r/wr controls the chip and secondary bus reset. 0: bridge is ready for operation 1: causes bridge to perform a chip reset 15:9 reserved r/o reserved. retu rns 0 when read. reset to 0. 14.1.31 arbiter control register ? offset 40h bit function type description 24:16 arbiter control r/w each bit controls whethe r a secondary bus master is assigned to the high priority group or the low priority group. bits [24:16] correspond to request inputs s_req[8:0] 0: low priority 1: high priority reset to 0 25 priority of secondary interface r/w controls whether the secondary in terface of the bridge is in the high priority group or the low priority group. 0: low priority 1: high priority reset to 1
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 87 of 112 july 2004 revision 1.00 bit function type description 26 broken master timeout enable r/w 0: broken master timeout off . if a master receives its gnt# active but does not initiate any transactions for more than 16 clocks, the arbiter will consider the master as broken for onl y two clocks. the current gnt# will be de-asserted if another master asse rts its req# or automatic preemption is on (bit[27] offset 40h); otherwis e the current gnt# will be kept asserted. 1: broken master timeout on . if a master receives its gnt# active but does not initiate any transactions for more than 16 clocks, the arbiter will consider the master as broken and the req# of the current master will be ignored for arbitration until de-asserti on of its req#. the current gnt# will be de-asserted if another master asserts its req# or automatic preemption is on (bit[27] offset 40h) ; otherwise the current gnt# will be kept asserted. reset to 0 27 automatic preemption control r/w 0: automatic preemption off . if the preemption timer expires (bit[31:28] offset 4ch) and another master asserts req#, the gnt# of the current master will be de-asserted and the gnt# of the next master will be asserted. if no other master asserts req#, the current gnt# will remain asserted. 1: automatic preemption on . if the preemption timer expires (bit[31:28] offset 4ch), the gnt# to the current master will be de- asserted for one clock. the same gn t# will be asserted again if no other master asserts its req#. if another master asserts its req#, the arbiter will generate a gnt# for the next master with the highest priority. reset to 0 31:28 reserved r/o returns 0000 when read. reset to 0000. 14.1.32 extended chip control register ? offset 48h bit function type description 0 memory read flow through disable r/w controls ability to do memory read flow through 0: enable flow through during a memory read transaction 1: disables flow through during a memory read transaction reset to 0 1 park r/w controls bus arbiter?s park function 0: park to last master 1: park to the bridge reset to 0 2 downstream (p to s) memory read dynamic prefetching r/w 0: enable downstream memory read prefetching dynamic control 1: disable downstream memory read prefetching dynamic control reset to 0 3 upstream (s to p) memory read dynamic prefetching r/w 0: enable upstream memory read prefetching dynamic control 1: disable upstream memory read prefetching dynamic control reset to 0
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 88 of 112 july 2004 revision 1.00 bit function type description 4 memory read underflow control r/w 0: bridge will start returning memory read data to the source bus after the 2 nd data is in the data buffer. if the data buffer is read as empty (underflow), bridge will insert target wait states (up to 7 wait states) on the source bus and prefetch more data in the data buffer. if there is no further data coming into the data buffer and the number of wait states reaches 7, the bridge will assert stop# to disconnect the master and terminate the transaction. 1: bridge will not start returning memory read data to the source bus until 1 cache line of data is accumulated in the data buffer. if the data buffer is read as empty (underflow), the br idge will stop prefetching at the destination bus and signal a disconnect to the external master on the source bus. the transaction entry and the associated data will be discarded. reset to 0 15:5 reserved r/o returns 0 when read. reset to 0. 14.1.33 upstream memory control register ? offset 48h bit function type description 16 upstream (s to p) memory base and limit enable r/w 0: upstream memory range is the entire range except the downstream memory channel 1: upstream memory range is confined to the upstream memory base and limit *see offset 58h, 5ch, and 60h for upstream memory range 31:17 reserved r/o returns 0 when read. reset to 0. 14.1.34 secondary bus arbiter preemption control register ? offset 4ch bit function type description 31:28 secondary bus arbiter preemption contorl r/w controls the number of clock cycles after frame is asserted before preemption is enabled. 1xxx: preemption off 0000: preemption enabled after 0 clock cycles after frame asserted 0001: preemption enabled after 1 cl ock cycle after frame asserted 0010: preemption enabled after 2 clock cycles after frame asserted 0011: preemption enabled after 4 clock cycles after frame asserted 0100: preemption enabled after 8 clock cycles after frame asserted 0101: preemption enabled after 16 cloc k cycles after frame asserted 0110: preemption enabled after 32 cloc k cycles after frame asserted 0111: preemption enabled after 64 cloc k cycles after frame asserted 14.1.35 hot swap switch time slot register ? offset 4ch bit function type description 27:0 hot swap switch time slot register r/w hot swap switch time slot set to 0003a98h (15k pci clocks). reset to 0003a98h.
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 89 of 112 july 2004 revision 1.00 14.1.36 eeprom autoload control / status register ? offset 50h bit function type description 15:0 reserved r/o returns 0 when read. reset to 0. 16 eeprom autoload control r/w 0: enable eeprom autoload 1: disable eeprom autoload reset to 0 17 fast eeprom autoload control r/w 0: normal speed of eeprom autoload 1: speeds up eeprom autoload by 32x reset to 0 18 eeprom autoload status r/o 0: eeprom autoload is not ongoing 1: eeprom autoload is on going reset to 0 31:19 reserved r/o returns 0 when read. reset to 0. 14.1.37 eeprom address / control register ? offset 54h bit function type description 0 eeprom read or write cycle start r/w 1 command for eeprom r/w controls the command sent to the eeprom 0: read 1: write reset to 0 2 eeprom error r/o 0: eeprom acknowledge is always received during the eeprom cycle. 1: eeprom acknowledge is not re ceived during the eeprom cycle. reset to 0 3 eeprom autoload complete status r/o 0: eeprom autoload is not successfully completed 1: eeprom autoload is successfully completed. reset to 0 5:4 reserved r/o returns 0 when read. reset to 0 7:6 eeprom clock frequency r/w 00: primary clock / 1024 01: primary clock / 512 10: primary clock / 256 11: primary clock / 32 reset to 0 8 reserved r/o returns 0 wh en read. reset to 0. 15:9 eeprom word address r/w stores the eeprom word address for the eeprom cycle. reset to 0 14.1.38 eeprom data register ? offset 54h bit function type description 31:16 eeprom data r/w stores the eeprom data to be wr itten into the eeprom or receives the data from the eeprom after an eeprom read cycle is completed.
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 90 of 112 july 2004 revision 1.00 14.1.39 upstream (s to p) memory ba se address register ? offset 58h bit function type description 3:0 64-bit addressing r/o 0000: 32-bit addressing 0001: 64-bit addressing reset to 0 15:4 upstream memory base r/w defines the bottom address of an addr ess range used by the bridge to determine when to forward ups tream memory transactions. reset to 0 14.1.40 upstream (s to p) memory li mit address register ? offset 58h bit function type description 19:16 64-bit addressing r/o 0000: 32-bit addressing 0001: 64-bit addressing reset to 0 31:20 upstream memory limit r/w defines the top address of an addr ess range used by the bridge to determine when to forward ups tream memory transactions. reset to 0 14.1.41 upstream (s to p) memory base address upper 32-bit register ? offset 5ch bit function type description 31:0 upstream memory base upper 32-bits r/w defines the upper 32-bits of a 64-bit bottom address of an address range for the bridge to determine when to forward upstream memory read and write transactions. reset to 0 14.1.42 upstream (s to p) memory limit address upper 32-bit register ? offset 60h bit function type description 31:0 upstream memory base upper 32-bits r/w defines the upper 32-bits of a 64-bit t op address of an address range for the bridge to determine when to fo rward upstream memory read and write transactions. reset to 0 14.1.43 p_serr# event disable register ? offset 64h bit function type description 0 reserved r/o returns 0 when read. reset to 0
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 91 of 112 july 2004 revision 1.00 bit function type description 1 posted write with parity error r/w 0: p_serr# is asserted if a parity error is detected on the target bus during a posted write transaction a nd the serr# enable bit in the command register is set. 1: p_serr# is not asserted, although a parity error is detected on the target bus during a posted write trans action and the serr# enable bit in the command register is set. reset to 0 2 posted write with non- delivery data r/w 0: p_serr# is asserted if the bridge is not able to transfer any posted write data after 2 24 attempts and the serr# en able bit in the command register is set. 1: p_serr# is not asserted although the bridge is not able to transfer any posted write data after 2 24 attempts and the serr# enable bit in the command register is set. reset to 0 3 target abort during posted write r/w 0: p_serr# is asserted if the br idge receives a target abort when attempting to deliver posted write data and the serr# enable bit in the command register is set. 1: p_serr# is not asserted even though the bridge receives a target abort when attempting to deliver poste d write data and the serr# enable bit in the command register is set. reset to 0 4 master abort during posted write r/w 0: p_serr# is asserted if the br idge receives a master abort when attempting to deliver posted write data and the serr# enable bit in the command register is set. 1: p_serr# is not asserted even though the bridge receives a master abort when attempting to deliver poste d write data and the serr# enable bit in the command register is set. reset to 0 5 delayed write with non- delivery r/w 0: p_serr# is asserted if the bridge is not able to transfer any delayed write data after 2 24 attempts and the serr# en able bit in the command register is set. 1: p_serr# is not asserted even tho ugh the bridge is not able to transfer any delayed write data after 2 24 attempts and the serr# enable bit in the command register is set. reset to 0 6 delayed read without data from target r/w 0: p_serr# is asserted if the bridge is not able to transfer any read data from the target after 2 24 attempts and the serr# enable bit in the command register is set. 1: p_serr# is not asserted even tho ugh the bridge is not able to transfer and read data from the target after 2 24 attempts and the serr# enable bit in the command register is set. reset to 0. 7 reserved r/o returns 0 wh en read. reset to 0.
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 92 of 112 july 2004 revision 1.00 14.1.44 gpio data and control register ? offset 64h bit function type description 11:8 gpio output write-1-to-clear r/wc setting any of these bits to 1 drives the corresponding bits low on the gpio[3:0] bus if it is programmed as bi -directional. data is driven on the pci clock cycle following completion of the configuration write to this register. the bit positions corresponding to the gpio pins that are programmed as input only are not driven. writing 0 to theses bits has no effect and will return the last writte n value when read. bits [11:8] correspond to gpio [3:0]. reset to 0 15:12 gpio output write-1-to-set r/ws setting any of these bits to 1 drives the corresponding bits high on the gpio[3:0] bus if it is programmed as bi -directional. data is driven on the pci clock cycle following completion of the configuration write to this register. the bit positions corresponding to the gpio pins that are programmed as input only are not driven. writing 0 to theses bits has no effect and will return the last writte n value when read . bits [15:12] correspond to gpio [3:0]. reset to 0 19:16 gpio output enable write-1- to-clear r/wc setting any of these bits to 1 configures the corresponding bits on the gpio[3:0] bus as input only. as a result, the output driver is tri-stated. writing 0 to theses bits has no effect and will return the last written value when read. bits [19:16] correspond to gpio [3:0]. reset to 0 23:20 gpio output enable write-1- to-set r/ws setting any of these bits to 1 configures the corresponding bits on the gpio[3:0] bus as bi-directional; the output driver is enabled and drives the value set in the output data regist er (offset 65h). writing 0 to theses bits has no effect and will return the last written value when read. bits [23:20] correspond to gpio [3:0]. reset to 0 27:24 reserved r/o returns 0 when read. reset to 0 31:28 gpio input data register r/o contains the state of the gpio[3:0] pins. state is updated on the pci clock cycle after any change to the state of the gpio[3:0] pins. reset to 0. 14.1.45 secondary clock control register ? offset 68h bit function type description 1:0 s_clkout[0] disable r/w s_clkout[0] (slot 0) enable 00: enable s_clkout[0] 01: enable s_clkout[0] 10: enable s_clkout[0] 11: disable s_clkout[0] and driven high reset to 00 3:2 s_clkout[1] disable r/w s_clkout[1] (slot 1) enable 00: enable s_clkout[1] 01: enable s_clkout[1] 10: enable s_clkout[1] 11: disable s_clkout[1] and driven high reset to 00
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 93 of 112 july 2004 revision 1.00 bit function type description 5:4 s_clkout[2] disable r/w s_clkout[2] (slot 2) enable 00: enable s_clkout[2] 01: enable s_clkout[2] 10: enable s_clkout[2] 11: disable s_clkout[2] and driven high reset to 00 7:6 s_clkout[3] disable r/w s_clkout[3] (slot 3) enable 00: enable s_clkout[3] 01: enable s_clkout[3] 10: enable s_clkout[3] 11: disable s_clkout[3] and driven high reset to 00 8 s_clkout[4] disable r/w s_clkout[4] (device 1) enable 0: enable s_clkout[4] 1: disable s_clkout[4] and driven high reset to 0 9 s_clkout[5] disable r/w s_clkout[5] (device 2) enable 0: enable s_clkout[5] 1: disable s_clkout[5] and driven high reset to 0 10 s_clkout[6] disable r/w s_clkout[6] (device 3) enable 0: enable s_clkout[6] 1: disable s_clkout[6] and driven high reset to 0 11 s_clkout[7] disable r/w s_clkout[7] (device 4) enable 0: enable s_clkout[7] 1: disable s_clkout[7] and driven high reset to 0 12 s_clkout[8] disable r/w s_clkout[8] (device 5) enable 0: enable s_clkout[8] 1: disable s_clkout[8] and driven high reset to 0 13 s_clkout[9] disable r/w s_clkout[9] (bridge) enable 0: enable s_clkout[4] 1: disable s_clkout[4] and driven high this bit is initialized upon secondary re set by shifting in a serial data stream. the bit is assigned to corre spond to the bridge secondary clock input (s_clkin). reset to 0 15:14 reserved ro returns 11 when read. reset to 11.
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 94 of 112 july 2004 revision 1.00 14.1.46 p_serr# status register ? offset 68h bit function type description 16 address parity error r/wc 1: signal p_serr# was asserted beca use an address parity error was detected on p or s bus. reset to 0 17 posted write data parity error r/wc 1: signal p_serr# was asserted becaus e a posted write data parity error was detected on the target bus. reset to 0 18 posted write non-delivery r/wc 1: signal p_serr# was asserted becaus e the bridge was unable to deliver post memory write data to the target after 2 24 attempts. reset to 0 19 target abort during posted write r/wc 1: signal p_serr# was asserted because the bridge received a target abort when delivering post memory write data. reset to 0. 20 master abort during posted write r/wc 1: signal p_serr# was asserted because the bridge received a master abort when attempting to deliver post memory write data reset to 0. 21 delayed write non-delivery r/wc 1: signal p_serr# was asserted becaus e the bridge was unable to deliver delayed write data after 2 24 attempts. reset to 0 22 delayed read ? no data from target r/wc 1: signal p_serr# was asserted beca use the bridge was unable to read any data from the target after 2 24 attempts. reset to 0. 23 delayed transaction master timeout r/wc 1: signal p_serr# was asserted because a master did not repeat a read or write transaction before master timeout. reset to 0. 31:24 reserved r/o returns 0 when read. reset to 0 14.1.47 port option register ? offset 74h bit function type description 0 reserved r/o returns 0 wh en read. reset to 0. 1 primary memory read command alias enable r/w 0: exact matching for non-posted memory write retry cycles from initiator on the primary interface 1: alias memrl or memrm to memr for memory read retry cycles from the initiator on the primary interface reset to 1 2 primary memory write command alias enable r/w reserved reset to 0 3 secondary memory read command alias enable r/w 0: exact matching for memory read retry cycles from initiator on the secondary interface 1: alias memrl or memrm to memr for memory read retry cycles from initiator on the secondary interface reset to 1
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 95 of 112 july 2004 revision 1.00 bit function type description 4 secondary memory write command alias enable r/w 0: exact matching for non-posted memory write retry cycles from initiator on the secondary interface 1: alias memwi to memw for non-pos ted memory write retry cycles from initiator on the secondary interface reset to 0 5 primary memory read line/multiple alias enable r/w 0: exact matching for memory read line/multiple retry cycles from initiator on the primary interface 1: alias memrl to memrm or memrm to memrl for memory read retry cycles from initiator on the primary interface reset to 1 6 secondary memory read line/multiple alias enable r/w 0: exact matching for memory read line/multiple retry cycles from initiator on the secondary interface 1: alias memrl to memrm or memrm to memrl for memory read retry cycles from initiato r on the secondary interface reset to 1 7 primary memory write and invalidate command alias disable r/w 0: when accepting memwi commands on primary, bridge converts memwi to memw on destination bus 1: when accepting memwi commands on primary, bridge does not convert memwi to memw on destination bus reset to 0 8 secondary memory write and invalidate command alias disable r/w 0: when accepting memwi commands on secondary, bridge converts memwi to memw on destination bus 1: when accepting memwi commands on secondary, bridge does not convert memwi to memw on destination bus reset to 0 9 enable long request r/w 0: normal lock operation 1: enable long request for lock cycle reset to 0 10 enable secondary to hold request longer r/w 0: internal secondary master will release req# after frame# assertion 1: internal secondary master will hold req# until there is no transactions pending in fifo or until terminated by target reset to 1 11 enable primary to hold request longer r/w 0: internal primary master will release req# after frame# assertion 1: internal primary master will hol d req# until there is no transactions pending in fifo or until terminated by target reset to 1 12 ordering rules control 1 r/w 0: enable the out of order capab ility between two dtr requests from two fifo?s 1: disable the out of order capab ility between two dtr requests from two fifo?s reset to 0
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 96 of 112 july 2004 revision 1.00 bit function type description 13 ordering rules control 2 r/w 0: keep the ordering rule require ments between delay read completion and posted write transactions 1: disregard the ordering rule requirements between delay read completion and posted write transactions reset to 0 15:14 reserved r/w reset to 0 14.1.48 secondary master timeout counter register ? offset 80h bit function type description 15:0 secondary master timeout r/w secondary timeout occurs after 2 15 pci clocks. reset to 8000h. 14.1.49 primary master timeout counter register ? offset 80h bit function type description 31:16 primary master timeout r/w primary timeout occurs after 2 15 pci clocks. reset to 8000h. 14.1.50 capability id register ? offset b0h bit function type description 7:0 enhanced capabilities id r/o read as 04h to indicate that these are slot indentification registers. 14.1.51 next pointer register ? offset b0h bit function type description 15:8 next item pointer r/o read as e8h. points to vital products data register. 14.1.52 slot number register ? offset b0h bit function type description 20:16 expansion slot number r/w indicates expansion slot number reset to 0 21 first in chassis r/w first in chassis reset to 0 23:22 reserved r/o returns 0 when read. reset to 0
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 97 of 112 july 2004 revision 1.00 14.1.53 chassis number register ? offset b0h bit function type description 31:24 chassis number r/w indicates chassis number reset to 0 14.1.54 capability id register ? offset dch bit function type description 7:0 enhanced capabilities id r/o read as 01h to indicate that these are power management enhanced capability registers. 14.1.55 next item pointer register ? offset dch bit function type description 15:8 next item pointer r/o read as b0h. points to slot number register. 14.1.56 power management capabilities register ? offset dch bit function type description 18:16 power management revision r/o read as 001 to indicate the device is compliant to revision 1.0 of pci power management interface specifications. 19 pme# clock r/o read as 0 to indicate bridge does not support the pme# pin. 20 auxiliary power r/o read as 0 to indicate bridge does not support the pme# pin or an auxiliary power source. 21 device specific initialization r/o read as 0 to indicate bridge does not have device specific initialization requirements. 24:22 reserved r/o read as 0 25 d1 power state support r/o read as 0 to indicate bridge does not support the d1 power management state. 26 d2 power state support r/o read as 0 to indicate bridge does not support the d2 power management state. 31:27 pme# support r/o read as 0 to indicate bridge does not support the pme# pin. 14.1.57 power management data register ? offset e0h bit function type description 1:0 power state r/w indicates the current power state of bridge. if an unimplemented power state is written to this register, bridge completes the write transaction, ignores the write data, and does not cha nge the value of the field. writing a value of d0 when the previous stat e was d3 cause a chip reset without asserting s_reset# 00: d0 state 01: d1 state (supported if bit[25] offset dch is high) 10: d2 state (supported if bit[26] offset dch is high) 11: d3 state reset to 0 7:2 reserved r/o read as 0 8 pme_l enable r/o read as 0 as bridge does not support the pme# pin.
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 98 of 112 july 2004 revision 1.00 bit function type description 12:9 data select r/o read as 0 as th e data register is not implemented. 14:13 data scale r/o read as 0 as the data register is not implemented. 15 pme status r/o read as 0 as the pme# pin is not implemented. 14.1.58 ppb support extensions register ? offset e0h bit function type description 21:16 reserved r/o reserved. reset to 0 22 b2_b3 r/o b2_b3 support for d3 hot : when bpcce is read as 1, this bit is driven as a logic level 1 to indicate that the secondary bus clock outputs will be stopped and driven low when the device is placed in d3 hot . this bit is undefined when bpcce is read as 0. 23 bus power/clock control enable r/o bus power / clock control enable: when the bpcce pin is tied high, this bit is read as a 1 to indi cate that the bus power/clock control mechanism is enabled. when the bpcce pin is tied low, this bit is read as a 0 to indicate that the bus power / clock control mechanism is disabled. 14.1.59 data register ? offset e0h bit function type description 31:24 data r/o data register: register is not implemented and is read as 00h. reset to 0. 14.1.60 capability id register ? offset e4h bit function type description 7:0 capability id r/o read as 06h to indicat e these are compactpci hot swap registers 14.1.61 next pointer register ? offset e4h bit function type description 15:8 next pointer r/o read as 00h to indicate end of pointer 14.1.62 hot swap control and status register ? offset e4h bit function type description 16 device hiding r/w 0: device hiding not armed 1: device hiding armed reset to 0 17 enum# signal mask r/w 0: mask enum# signal 1: enable enum# signal reset to 0 18 pending insertion / extraction r/o 0: ins is not armed and neither ins nor ext has a value of 1 1: either ins or ext has a value of 1 or ins is armed reset to 0 19 led on/off r/w 0: led on 1: led off reset to 0
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 99 of 112 july 2004 revision 1.00 bit function type description 21:20 pi (programming interface) r/o read as 01 to indicate in addition to the features of programming interface 0, device hiding, the dha bit and the pie bit are implemented 22 ext (enum# status ? extraction) r/wc 0: enum# is not asserted 1: enum# is asserted reset to 0 23 ins (enum# status ? insertion) r/wc 0: enum# is not asserted 1: enum# is asserted reset to 0 31:24 reserved r/o returns 0 when read. reset to 0 14.1.63 capability id register ? offset e8h bit function type description 7:0 capability id r/o read as 03h to indicate these are vpd registers 14.1.64 next pointer register ? offset e8h bit function type description 15:8 next pointer r/o e4: hs_en is 1 00: hs_en is 0 14.1.65 vpd register ? offset e8h bit function type description 17:16 reserved r/o returns 0 when read. reset to 0 23:18 vpd address r/w vpd address for read / write cycle 30:24 reserved r/o returns 0 when read. reset to 0 31 vpd operation r/w writing a 0 to this bit generates a read cycle from the eeprom at the vpd address specified in bits[7:2] of this register. this bit remains 0 until eeprom cycle is finished, after wh ich it will be set to 1. data for reads are available at offset ech. writing a 1 to this bit generates a wr ite cycle to the eeprom at the vpd address specified in bits[7:2] of this register. this bit remains at 1 until eeprom cycle is finished, after which it will be cleared to 0. reset to 0 14.1.66 vpd data register ? offset ech bit function type description 31:0 vpd data r/w vpd data (eeprom data [address + 0x40]. the least significant byte of this regi ster corresponds to the byte of vpd at the address specified by the vpd address register. the data from or written to this register uses the normal pci byte tr ansfer capabilities. reset to 0
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 100 of 112 july 2004 revision 1.00 15 bridge behavior a pci cycle is initiated by asserting the frame# signal. in a bridge, there are a number of possibilities. those possibilities are summarized in the table below: 15.1 bridge actions for various cycle types initiator target response master on primary target on primary pi7c8154a does not respond. it detects this situation by decoding the address as well as monitoring the p_devsel# for other fast and medium devices on the primary port. master on primary target on secondary pi7c8154a asserts p_devsel#, terminates the cycle normally if it is able to be posted, otherwise return with a re try. it then passes the cycle to the appropriate port. when the cycle is complete on the target port, it will wait for the initiator to repeat the same cycle and end with normal termination. master on primary target not on primary nor secondary port pi7c8154a does not respond and the cycle will terminate as master abort. master on secondary target on the same secondary port pi7c8154a does not respond. master on secondary target on primary or the other secondary port pi7c8154a asserts s_devsel#, terminates the cycle normally if it is able to be posted, otherwise returns with a retry. it then passes the cycle to the appropriate port. when cycle is complete on the target port, it will wait for the initiator to repeat the same cycle and end with normal termination. master on secondary target not on primary nor the other secondary port pi7c8154a does not respond. 15.2 abnormal termination (initiated by bridge master) 15.2.1 master abort master abort indicates that when pi7c8154a acts as a master and receives no response (i.e., no target asserts devsel# or s_devsel#) from a target, the bridge deasserts frame# and then de-asserts irdy#. 15.2.2 parity and error reporting parity must be checked for all addresses and write data. parity is defined on the p_par, p_par64, s_par, and s_par64 signals. parity should be even (i. e. an even number of?1?s) across ad, cbe, and par. parity information on par is va lid the cycle after ad and cbe are valid. for reads, even parity must be generated using the initiators cbe signals combined with the read data. again, the par signal corresponds to read da ta from the previous data phase cycle.
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 101 of 112 july 2004 revision 1.00 15.2.3 reporting parity errors for all address phases, if a parity error is dete cted, the error should be reported on the p_serr# signal by asserting p_serr# for one cycle and then tri-stating two cycles after the bad address. p_serr# can only be asserted if bit 6 and 8 in the command register are both set to 1. for write data phases, a parity error should be reported by asserting the p_perr# signal two cycles after the data phase and should remain asserted for one cycl e when bit 6 in the command register is set to a 1. the target reports any type of data parity errors during write cycles, while the master reports data parity errors during read cycles. detection of an address parity error will cause the pci-to-pci bridge target to not claim the bus (p_devsel# remains inactive) and the cycle will th en terminate with a master abort. when the bridge is acting as master, a data parity error du ring a read cycle results in the bridge master initiating a master abort. 15.2.4 secondary idsel mapping when pi7c8154a detects a type 1 configuratio n transaction for a device connected to the secondary, it translates the type 1 transa ction to type 0 transaction on the downstream interface. type 1 configuration format uses a 5-b it field at p_ad[15:11] as a device number. this is translated to s_ad[31:16] by pi7c8154a. 16 ieee 1149.1 compatible jtag controller an ieee 1149.1 compatible test access port (t ap) controller and associated tap pins are provided to support boundary scan in pi7c8154a for board-level continuity test and diagnostics. the tap pins assigned are tck, tdi, tdo, tms and trst#. all digital input, output, input/output pins are tested except tap pins. the ieee 1149.1 test logic consists of a tap controller, an instruction register, and a group of test data registers including bypass and boundary scan registers. the tap controller is a synchronous 16-state machine driven by the test clock (tck) and the test mode select (tms) pins. an independent power on reset circuit is provided to ensure the machine is in test_logic_reset state at power-up. the jtag signal lines are not active when the pci resource is operating pci bus cycles. pi7c8154a implements 3 basic instructions: bypass, sample/preload, and extest. 16.1 boundary scan architecture boundary-scan test logic consists of a boundary-s can register and support logic. these are accessed through a test access port (tap). the tap provides a simple se rial interface that allows all processor signal pins to be driven and/or sampled, thereby providing direct control and monitoring of processor pins at the system level. this mode of operation is valuable for design debugging and fault diagnosis since it permits examination of connections not normally accessible to the test system. the following subsections
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 102 of 112 july 2004 revision 1.00 describe the boundary-scan test logic elements: ta p pins, instruction register, test data registers and tap controller. figure 16-1 illustrates how thes e pieces fit together to form the jtag unit. figure 16-1 test access port diagram 16.1.1 tap pins the pi7c8154a?s tap pins form a serial port composed of four input connections (tms, tck, trst# and tdi) and one output connection (tdo). these pins are described in table 16-1. the tap pins provide access to the instruction register and the test data registers. 16.1.2 instruction register the instruction register (ir) holds instruction code s. these codes are shifted in through the test data input (tdi) pin. the instruction codes are us ed to select the specific test operation to be performed and the test data register to be accessed. the instruction register is a parallel-loadable, master/slave-configured 5- bit wide, serial-shift register with latched outputs. data is shifted in to and out of the ir serially through the tdi pin clocked by the rising edge of tck. the shifted-in instruction becomes active upon latching from the master stage to the slave stag e. at that time the ir outputs along with the tap finite state machine outputs are decoded to select and control the test data register selected by that instruction. upon latching, all actions caused by any previous instructions terminate. the instruction determines the test to be performed, the test data register to be accessed, or both. the ir is two bits wide. when the ir is selected, the most significant bit is connected to tdi, and the least significant bit is connected to tdo. the value presented on the tdi pin is shifted into the ir on each rising edge of tck. the tap controller captures fixed parallel data (1101 binary). when a new instruction is shifted in through td i, the value 1101(binary) is always shifted out through tdo, least significant bit first. this helps id entify instructions in a long chain of serial data from several devices.
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 103 of 112 july 2004 revision 1.00 upon activation of the trst# reset pin, the latched instruction asynchronously changes to the id code instruction. when the tap controller moves into the test state other than by reset activation, the opcode changes as tdi shifts, and becomes active on the falling edge of tck. 16.2 boundary scan instruction set the pi7c8154a supports three mandatory boundary-scan instructions (bypass, sample and extest). table 16-1 shown below lists the pi7c8154a?s boundary-scan instruction codes. table 16-1 tap pins instruction / requisite opcode (binary) description extest ieee 1149.1 required 00000 extest initiates testing of extern al circuitry, typically board-level interconnects and off chip circuitry. extest connects the boundary- scan register between tdi and tdo. when extest is selected, all output signal pin values are driven by values shifted into the boundary- scan register and may change only of the falling edge of tck. also, when extest is selected, all system input pin states must be loaded into the boundary-scan register on the rising-edge of tck. sample ieee 1149.1 required 0001 sample performs two functions: ! a snapshot of the sample instruction is captured on the rising edge of tck without interferi ng with normal operation. the instruction causes boundary-scan register cells associated with outputs to sample the value being driven. ! on the falling edge of tck, the data held in the boundary-scan cells is transferred to the slave register cells. typically, the slave latched data is applied to the system outputs via the extest instruction. intscan 00010 enable internal scan test clamp 00100 clamp instruction allows the state of the signals driven from component pins to be determined from the boundary-scan register while the bypass register is selected as the serial path between tdi and tdo. the signal driven from the component pins will not change while the clamp instruction is selected. bypass 11111 bypass instruction selects th e one-bit bypass register between tdi and tdo pins. 0 (binary) is the only instruction that accesses the bypass register. while this instructi on is in effect, all other test data registers have no effect on system ope ration. test data registers with both test and system functionality performs their system functions when this instruction is selected. 16.3 tap test data registers the pi7c8154a contains two test data registers (bypass and boundary-scan). each test data register selected by the tap controller is connected serially between tdi and tdo. tdi is connected to the test data register?s most signifi cant bit. tdo is connected to the least significant bit. data is shifted one bit position within the re gister towards tdo on each rising edge of tck. while any register is selected, data is transf erred from tdi to tdo without inversion. the following sections describe each of the test data registers.
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 104 of 112 july 2004 revision 1.00 16.4 bypass register the required bypass register, a on e-bit shift register, provides the shortest path between tdi and tdo when a bypass instruction is in effect. this allows rapid movement of test data to and from other components on the board. this path can be selected when no test operation is being performed on the pi7c8154a. 16.5 boundary scan register the boundary-scan register contains a cell for each pin as well as control cells for i/o and the high- impedance pin. table 16-2shows the bit order of the pi7c8154a boundary-scan register. all table cells that contain ?control? sel ect the direction of bi-directional pins or high-impedance output pins. when a ?1? is loaded into the control ce ll, the associated pin(s) are high-impedance or selected as output. the boundary-scan register is a required set of serial-shiftable register cells, configured in master/slave stages and connected between each of the pi7c8154a?s pins and on-chip system logic. the vdd, gnd, and jtag pins are not in the boundary-scan chain. the boundary-scan register cells are dedicated logic and do not have any system function. data may be loaded into the boundary-scan register master cells from the device input pins and output pin-drivers in parallel by the mandatory sample and extest instructions. parallel loading takes place on the rising edge of tck. data may be scanned into the boundary-scan register serially via the tdi serial input pin, clocked by the rising edge of tck. when the required data has been loaded into the master-cell stages, it can be driven into the system logic at input pins or onto the output pins on the falling edge of tck state. data may also be shifted out of the boundary-scan register by means of the tdo serial output pin at the falling edge of tck. 16.6 tap controller the tap (test access port) controller is a 4-state synchronous finite state machine that controls the sequence of test logic operations. the tap can be controlled via a bus master. the bus master can be either automatic test equipment or a com ponent (i.e., pld) that interfaces to the tap. the tap controller changes state only in response to a rising edge of tck. the value of the test mode state (tms) input signal at a risi ng edge of tck controls the sequence of state changes. the tap controller is initialized after power-up by applyi ng a low to the trst# pin. in addition, the tap controller can be initialized by applying a high signal level on the tms input for a minimum of five tck periods. for greater detail on the behavior of the tap contro ller, test logic in each controller state and the state machine and public instructions, refer to the ieee 1149 .1 standard test access port and boundary-scan architecture document (available from the ieee).
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 105 of 112 july 2004 revision 1.00 table 16-2 jtag boundary register order boundary-scan register number pin name ball location type 0 s_par64 n21 bidir 1 s_ad[32] m21 bidir 2 s_ad[33] m23 bidir 3 s_ad[34] m22 bidir 4 s_ad[35] l22 bidir 5 s_ad[36] l21 bidir 6 s_ad[37] l23 bidir 7 s_ad[38] k21 bidir 8 s_ad[39] k22 bidir 9 s_ad[40] k23 bidir 10 s_ad[41] j22 bidir 11 s_ad[42] j20 bidir 12 s_ad[43] j23 bidir 13 s_ad[44] h21 bidir 14 s_ad[45] h22 bidir 15 s_ad[46] h23 bidir 16 s_ad[47] g21 bidir 17 s_ad[48] g22 bidir 18 s_ad[49] g20 bidir 19 s_ad[50] f22 bidir 20 s_ad[51] f23 bidir 21 s_ad[52] f21 bidir 22 s_ad[53] e23 bidir 23 s_ad[54] e21 bidir 24 s_ad[55] d22 bidir 25 s_ad[56] e20 bidir 26 s_ad[57] d21 bidir 27 s_ad[58] c22 bidir 28 s_ad[59] c23 bidir 29 s_ad[60] c21 bidir 30 s_ad[61] d20 bidir 31 s_ad[62] a21 bidir 32 s_ad[63] c20 bidir 33 s_cbe[4] d19 bidir 34 s_cbe[5] a20 bidir 35 s_cbe[6] c19 bidir 36 s_cbe[7] a19 bidir 37 s_req64# b19 bidir 38 s_ack64# c18 bidir 39 s_ad[0] a18 bidir 40 s_ad[1] b18 bidir 41 s_ad[2] a17 bidir 42 s_ad[3] d17 bidir 43 s_ad[4] b17 bidir 44 s_ad[5] c17 bidir 45 s_ad[6] b16 bidir 46 s_ad[7] c16 bidir 47 s_cbe[0] a15 bidir 48 s_ad[8] b15 bidir 49 s_ad[9] c15 bidir 50 s_m66en a14 bidir 51 s_ad[10] b14 bidir 52 s_ad[11] c14 bidir 53 s_ad[12] d13 bidir 54 s_ad[13] a13 bidir 55 s_ad[14] b13 bidir 56 s_ad[15] c13 bidir 57 s_cbe[1] c12 bidir 58 * control
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 106 of 112 july 2004 revision 1.00 boundary-scan register number pin name ball location type 59 s_par b12 bidir 60 s_serr# b11 input 61 s_perr# c11 bidir 62 s_lock# a11 bidir 63 s_stop# c10 bidir 64 s_devsel# b10 bidir 65 s_trdy# a10 bidir 66 s_irdy# c9 bidir 67 * control 68 s_frame# b9 bidir 69 s_cbe[2] d9 bidir 70 s_ad[16] a9 bidir 71 s_ad[17] c8 bidir 72 s_ad[18] b8 bidir 73 s_ad[19] a8 bidir 74 s_ad[20] b7 bidir 75 s_ad[21] d7 bidir 76 s_ad[22] a7 bidir 77 s_ad[23] a6 bidir 78 s_cbe[3] c6 bidir 79 s_ad[24] b5 bidir 80 s_ad[25] c5 bidir 81 s_ad[26] b4 bidir 82 s_ad[27] a4 bidir 83 s_ad[28] c4 bidir 84 s_ad[29] b3 bidir 85 s_ad[30] a3 bidir 86 * control 87 s_ad[31] c3 bidir 88 s_req#[0] d4 input 89 s_req#[1] c1 input 90 s_req#[2] c2 input 91 s_req#[3] d3 input 92 s_req#[4] e4 input 93 s_req#[5] d1 input 94 s_req#[6] d2 input 95 s_req#[7] e3 input 96 s_req#[8] e1 input 97 s_gnt#[0] e2 bidir 98 s_gnt#[1] f3 bidir 99 s_gnt#[2] f1 bidir 100 s_gnt#[3] f2 bidir 101 * control 102 s_gnt#[4] g1 bidir 103 s_gnt#[5] g4 bidir 104 s_gnt#[6] g2 bidir 105 s_gnt#[7] g3 bidir 106 s_gnt#[8] h1 bidir 107 s_reset# h2 bidir 108 s_clkin j4 input 109 s_cfn# k1 input 110 gpio[3] k2 bidir 111 gpio[2] k3 bidir 112 gpio[1] l4 bidir 113 gpio[0] l1 bidir 114 s_clkout[0] l2 output 115 * control 116 s_clkout[1] l3 output 117 s_clkout[2] m3 output 118 s_clkout[3] m1 output 119 s_clkout[4] m2 output 120 s_clkout[5] n3 output
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 107 of 112 july 2004 revision 1.00 boundary-scan register number pin name ball location type 121 s_clkout[6] n1 output 122 s_clkout[7] p3 output 123 s_clkout[8] p2 output 124 s_clkout[9] p1 output 125 p_reset# r3 input 126 p_gnt# r2 input 127 bpcce r4 input 128 p_clk t3 input 129 * control 130 p_req# u3 bidir 131 p_ad[31] u2 bidir 132 p_ad[30] u4 bidir 133 p_ad[29] u1 bidir 134 p_ad[28] v2 bidir 135 p_ad[27] v1 bidir 136 p_ad[26] v3 bidir 137 p_ad[25] w2 bidir 138 p_ad[24] w1 bidir 139 p_cbe[3] y2 bidir 140 p_idsel] y1 input 141 p_ad[23] w4 bidir 142 p_ad[22] y3 bidir 143 p_ad[21] aa1 bidir 144 p_ad[20] aa3 bidir 145 p_ad[19] y4 bidir 146 p_ad[18] ab3 bidir 147 p_ad[17] aa4 bidir 148 p_ad[16] y5 bidir 149 * control 150 p_cbe[2] ab4 bidir 151 p_frame# aa5 bidir 152 p_irdy# ac5 bidir 153 p_trdy# ab5 bidir 154 p_devsel# aa6 bidir 155 p_stop# ac6 bidir 156 p_lock# ab6 input 157 * control 158 p_perr# ac7 bidir 159 p_serr# y7 output 160 p_par ab7 bidir 161 p_cbe[1] aa7 bidir 162 p_ad[15] ab8 bidir 163 p_ad[14] aa8 bidir 164 p_ad[13] ac9 bidir 165 p_ad[12] ab9 bidir 166 p_ad[11] aa9 bidir 167 p_ad[10] ac10 bidir 168 p_m66en ab10 input 169 p_ad[9] aa10 bidir 170 p_ad[8] y11 bidir 171 p_cbe[0] ac11 bidir 172 p_ad[7] ab11 bidir 173 p_ad[6] aa11 bidir 174 p_ad[5] aa12 bidir 175 p_ad[4] ab12 bidir 176 p_ad[3] ab13 bidir 177 p_ad[2] aa13 bidir 178 p_ad[1] y13 bidir 179 p_ad[0] aa14 bidir 180 p_ack64# ab14 bidir 181 p_req64# ac14 bidir 182 p_cbe[7] aa15 bidir
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 108 of 112 july 2004 revision 1.00 boundary-scan register number pin name ball location type 183 p_cbe[6] ab15 bidir 184 p_cbe[5] y15 bidir 185 p_cbe[4] ac15 bidir 186 p_ad[63] aa16 bidir 187 p_ad[62] ab16 bidir 188 p_ad[61] aa17 bidir 189 p_ad[60] ab17 bidir 190 p_ad[59] y17 bidir 191 p_ad[58] ab18 bidir 192 p_ad[57] ac18 bidir 193 p_ad[56] aa18 bidir 194 p_ad[55] ac19 bidir 195 p_ad[54] aa19 bidir 196 p_ad[53] ab20 bidir 197 p_ad[52] y19 bidir 198 p_ad[51] aa20 bidir 199 p_ad[50] ab21 bidir 200 p_ad[49] ac21 bidir 201 p_ad[48] aa21 bidir 202 p_ad[47] y20 bidir 203 p_ad[46] aa23 bidir 204 p_ad[45] y21 bidir 205 p_ad[44] w20 bidir 206 p_ad[43] y23 bidir 207 p_ad[42] w21 bidir 208 p_ad[41] w23 bidir 209 p_ad[40] w22 bidir 210 p_ad[39] v21 bidir 211 p_ad[38] v23 bidir 212 p_ad[37] v22 bidir 213 p_ad[36] u23 bidir 214 p_ad[35] u20 bidir 215 p_ad[34] u22 bidir 216 * control 217 p_ad[33] t23 bidir 218 p_ad[32] t22 bidir 219 p_par64 t21 bidir 220 config66 r22 input 221 msk_in r21 input
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 109 of 112 july 2004 revision 1.00 17 electrical and timing specifications 17.1 maximum ratings (above which the useful life may be impaired. for user guidelines, not tested). storage temperature -65 c to 150 c ambient temperature with power applied 0 c to 85 c supply voltage to ground potentials (av cc and v dd only] -0.3v to 3.6v voltage at input pins -0.5v to 5.5v junction temperature, t j 125 c note: stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and func tional operation of the device at these or any conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. 17.2 dc specifications symbol parameter condition min. max. units notes v dd supply voltage 3 3.6 v v ih input high voltage 0.7 v dd v dd + 0.5 v 1 v il input low voltage -0.5 0.3 v dd v 1 v oh output high voltage i out = -500 a 0.9v dd v v ol output low voltage i out = 1500 a 0.1 v dd v v oh5v 5v signaling output high voltage i out = -2 ma 2.4 v v ol5v 5v signaling output low voltage i out = 6 ma 0.5 v i il input leakage current 0 < v in < v dd 10 a c in input pin capacitance 10 pf c clk clk pin capacitance 5 12 pf c idsel idsel pin capacitance 8 pf l pin pin inductance 20 nh notes: 1. v dd is in reference to the v dd of the input device. 17.3 ac specifications figure 17-1 pci signal timing measurement conditions
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 110 of 112 july 2004 revision 1.00 66 mhz 33 mhz symbol parameter min. max. min. max . units tsu input setup time to clk ? bused signals 1,2,3 3 - 7 - tsu(ptp) input setup time to clk ? point-to-point 1,2,3 5 - 10, 12 4 - th input signal hold time from clk 1,2 0 - 0 - tval clk to signal valid delay ? bused signals 1,2,3 2 6 2 11 tval(ptp) clk to signal valid delay ? point-to-point 1,2,3 2 6 2 12 ton float to active delay 1,2 2 - 2 - toff active to float delay 1,2 - 14 - 28 ns 1. see figure 17-1 pci signal timing measurement conditions. 2. all primary interface signals are synchronized to p_clk. all secondary interface signals are synchronized to s_clkout. 3. point-to-point signals are p_req#, s_req#[7:0], p_gnt#, s_gnt#[7:0], hsled, hs_sw#, hs_en, and enum#. bused signals are p_ad, p_bde#, p_par, p_perr#, p_serr#, p_frame#, p_irdy#, p_trdy#, p_lock#, p_devsel#, p_stop#, p_idsel, p_par64, p_req64#, p_ack64#, s_ad, s_cbe#, s_par, s_perr#, s_serr#, s_frame#, s_irdy#, s_trdy#, s_lock#, s_devs el#, s_stop#, s_pa64, s_req64#, and s_ack64#. 4. req# signals have a setup of 10ns and gnt# signals have a setup of 12ns. 17.4 66mhz pci signaling timing symbol parameter condition min. max. units t skew skew among s_clkout[9:0] 0 0.250 t delay delay between pclk and s_clkout[9:0] 20pf load 3.47 4.20 t cycle p_clk, s_clkout[9:0] cycle time 15 30 t high p_clk, s_clkout[9:0] high time 6 t low p_clk, s_clkout[9:0] low time 6 ns 17.5 33mhz pci signaling timing symbol parameter condition min. max. units t skew skew among s_clkout[9:0] 0 0.250 t delay delay between pclk and s_clkout[9:0] 20pf load 3.47 4.20 t cycle p_clk, s_clkout[9:0] cycle time 30 t high p_clk, s_clkout[9:0] high time 11 t low p_clk, s_clkout[9:0] low time 11 ns 17.6 reset timing symbol parameter min. max. units t rst p_reset# active time after power stable 1 - us t rst-clk p_reset# active time after p_clk stable 100 - us t rst-off p_reset# active-to-output float delay - 40 ns t srst s_reset# active after p_reset# assertion - 40 ns t srst-on s_reset# active time after s_clkin stable 100 - us t drst s_reset# deassertion after p_ reset# deassertion 20 25 cycles
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 111 of 112 july 2004 revision 1.00 17.7 gpio timing (66mhz & 33mhz) symbol parameter min. max. units t vgpio s_clkin to gpio output valid 2 12 ns t gon gpio float to output valid 2 - ns t gof f gpio active to float delay - 28 ns t gsu gpio-to-s_clkin setup time 7 - ns t gh gpio hold time after s_clkin 0 - nx t gcval s_clkin-to-gpio shift clock output valid - 13.5 ns t gcyc gpio[0] cycle time 30 ns t gsval gpio[0] to gpio[2] shift control output valid - 8 ns t msu msk_in setup time to gpio[0] 15 - ns t mh msk_in hold time after gpio[0] 0 - ns 17.8 jtag timing symbol parameter min. max. units t if tck frequency 0 10 mhz t jp tck period 100 ns t jht tck high time 45 - ns t jlt tck low time 45 - ns t jrt tck rise time 1 - 10 ns t jft tck fall time 2 - 10 ns t je tdi, tms setup time to tck rising edge 10 - ns t jh tdi, tms hold time from tck rising edge 25 - ns t jd tdo valid delay from tck falling edge 3 - 30 ns t jfd tdo float delay from tck falling edge - 30 ns 1. measured between 0.8v to 2.0v 2. measured between 2.0v to 0.8v 3. c1=50pf 17.9 power consumption parameter typical units power consumption at 66mhz 1.38 w supply current, i cc 417 ma
pi7c8154a asynchronous 2-port pci-to-pci bridge advance information page 112 of 112 july 2004 revision 1.00 18 package information 18.1 304-ball pbga pa ckage diagram figure 18-1 304-ball pbga package outline thermal characteristics can be found on the web: http://www.pericom.com/packaging/mechanicals.php 18.2 ordering information part number speed pin ? package temperature pi7c8154ana 66mhz 304 ? pbga 0c to 85c pi7c8154anae 66mhz 304 ? pbga (p b-free & green) 0c to 85c PI7C8154ANA-33 33mhz 304 ? pbga 0c to 85c pi7c8154anae-33 33mhz 304 ? pbga (pb-free & green) 0c to 85c

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